82546GB Datasheet, PDF (10/16 Pages) Intel Corporation – Gigabit Ethernet Controller Specification Update

82546GB GIGABIT ETHERNET CONTROLLER SPECIFICATION UPDATE
4. Message Signaled Interrupt Feature May Corrupt Write Transactions
Problem:
Implication:
Workaround:
Status:
The problem is with the implementation of the Message Signaled Interrupt (MSI) feature in the Ethernet
controller. During MSI writes, the controller should use the MSI message data value in PCI configuration space.
At the same time, for normal write transactions (received packet data and/or descriptor writebacks), the
controller temporarily stores the data for write transactions in a small memory until it is granted ownership of the
PCI/PCI-X bus. The error condition occurs when during the MSI operation the controller incorrectly pulls data
from the memory storing the data waiting to be written. If there are any write transactions waiting when this
occurs, these transactions may become corrupted. This, in turn, may cause the network controller to lock up
and become unresponsive.
If the affected products are used with an OS that utilizes Message Signal Interrupts and no accommodations are
made to mitigate the use of these interrupts, data integrity issues may occur.
For PCI systems, advertisement of the MSI capability can be turned off by setting the MSI Disable bit in the
EEPROM (Init Control Word 2, bit 7).
For PCI-X systems where MSI support is enumerated as part of the PCI-X specification, Intel is working with OS
vendors to ensure that any future implementations of their operating systems can detect these products and
avoid using the MSI mechanism. Further details will be communicated as they become available.
Intel does not plan to resolve this erratum in a future stepping of the 82546GB Gigabit Ethernet Controller.
5. Link Establishment or Communication Problems in Fiber Mode When Link
Partner Does Not Fully Comply with the IEEE 802.3 Specification
Problem:
Implication:
Workaround:
Status:
The following minor compliance issues have been discovered between the TBI/SERDES mode symbol
synchronization logic and the IEEE specification:
- When presented with short sequences of malformed code groups, the receive synchronization logic within the
Ethernet controller may acquire & indicate link/synchronization prematurely or incorrectly
- When presented with certain short sequences of malformed code groups, the logic may retain
link/synchronization indication through the error sequence instead of immediately detecting and dropping
link/synchronization
- With some specific erroneous sequences of code groups, the auto-negotiation logic may establish link in
certain very specific situations where the specification says it should not
- Finally, the receive error detection logic may not detect and count some symbol errors when malformed idle
patterns are received.
If a link partner is not compliant with the IEEE 802.3 Specification in certain very specific ways, the 82546GB
controller may not be able to establish link or communicate properly with it. If the controller is tested for strict
compliance with the IEEE 802.3 Specification, it may fail some of the Clause 36 and Clause 37 test cases.
However, Intel has performed extensive compatibility testing as an integral part of controller HW validation, and
continues to do so with the latest Ethernet devices. To date, these issues have not been shown to cause
interoperability problems with any Ethernet devices currently in production.
None.
Intel does not plan to resolve this erratum in a future stepping of the 82546GB Gigabit Ethernet Controller.
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