82546GB Datasheet, PDF(7/16 Page) Intel Corporation – Gigabit Ethernet Controller Specification Update

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82546GB Datasheet, PDF (7/16 Pages) Intel Corporation – Gigabit Ethernet Controller Specification Update

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82546GB GIGABIT ETHERNET CONTROLLER SPECIFICATION UPDATE

SUMMARY TABLE OF CHANGES

The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply

to the listed 82546GB steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the

other outstanding issues through documentation or Specification Changes as noted. This table uses the following notations:

CODES USED IN SUMMARY TABLES

Doc:

Fix:

Fixed:

NoFix:

(No mark) or (Blank Box):

Shaded:

Erratum, Specification Change or Clarification that applies to this stepping.

Document change or update that will be implemented.

This erratum is intended to be fixed in a future stepping of the component.

This erratum has been previously fixed.

There are no plans to fix this erratum.

This erratum is fixed in listed stepping or specification change does not apply to listed stepping.

This item is either new or modified from the previous version of the document.

No. A0

10 X

11 X

12 X

13 x

14 x

15 X

Plans

NoFix

ERRATA

LSO Premature Descriptor Write Back

XOFF from Link Partner can Pause Flow-Control (XON/XOFF)

Transmission

Transmit Descriptor use of RS for non-data (Context & Null)

Descriptors

Message Signaled Interrupt Feature May Corrupt Write

Transactions

Link Establishment or Communication Problems in Fiber Mode

When Link Partner Does Not Fully Comply with the IEEE 802.3

Specification

Wakeup Packet Memory (WUPM) cleared upon reset

Unexpected RMCP ACK packets in ASF mode

Exceeding PCI Power Management Specification Limit of 375

mA current during reset and power state transitions

Inbound and Outbound reads not fully decoupled in PCI-X

mode

Hang in PCI-X systems due to 2k buffer overrun during transmit

operation

CRC Errors due to Rate Adaptation FIFO Overflow in Fiber

Mode

PCI-X Arbitration Interaction with Particular Bridges Can Result

in Controller Hang

Transmit Descriptors May Be Written Back to Host, Even

Without the RS Bit Set

Legacy Transmit Descriptor Write-Back May Occur Before the

Packet Data Associated with the Descriptor is Fetched

PCI-X Burst Write Transactions to Memory Mapped Registers at

Non-Qword-Aligned Offsets Fail

Page

Notes

New

No. A0

Plans

NoFix

SPECIFICATION CLARIFICATIONS

82546GB Ports Can be Disabled Individually

Page

Notes

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