82546GB Datasheet, PDF (13/16 Pages) Intel Corporation – Gigabit Ethernet Controller Specification Update

82546GB GIGABIT ETHERNET CONTROLLER SPECIFICATION UPDATE
12. PCI-X Arbitration Interaction with Particular Bridges Can Result in Controller
Hang
Problem:
Implication:
In PCI-X mode, the 82546GB arbitration logic de-asserts its REQ# signal briefly before beginning a transaction.
This is permitted by the PCI-X specification but is not optimal behavior.
Under a very specific set of circumstances, certain PCI-X bridge components might respond to this behavior in a
way that hangs the system. If the PCI-X bridge sees the 82546GB de-asserting REQ# then it might choose to
immediately de-assert GNT#. The 82546GB will then abandon its attempt to begin a transaction and re-start its
arbitration cycle. If this cycle happens repeatedly, the 82546GB might be unable to initiate PCI-X transactions.
Workaround:
The 82546GB interoperates well with the majority of PCI-X bridge components. However, the Intel® 31154
PCI-X-to-PCI-X bridge exhibits the behavior described above. Systems that use both components in PCI-X
mode will need to implement one of the following workarounds.
This issue can be addressed in several ways:
1. Operate the bus segment containing the 82546GB in PCI mode. The erratum does not occur in PCI mode.
2. Configure the arbiter in the PCI-X Bridge to change its arbitration behavior. Changing something as small as
the master on which it parks can alter timings enough to avoid the problem.
3. Add a Programmable Logic Device (PLD) to your application to detect this situation and break the deadlock
by changing the duration of the 82546GB's REQ# assertion.
Status:
For further details on these options, including sample code for a Programmable Logic Device, see TA-176
("Possible System Hang When Using an Intel® 82546GB LAN Controller with Certain PCI Bridges”).
Intel does not plan to resolve this erratum in a future stepping of the 82546GB Gigabit Ethernet Controller.
13. Transmit Descriptors May Be Written Back to Host, Even Without the RS Bit
Set
Problem:
Implication:
Workaround:
Status:
If the RS bit is set on at least some transmit descriptors submitted to the device, it is possible that some other
transmit descriptors without the RS bit set will be incorrectly written back to host memory.
The unnecessary descriptor write-backs will not cause a functional issue, but they may result in a small amount
of unnecessary host bus bandwidth to be consumed.
None.
Intel does not plan to resolve this erratum in a future stepping of the 82546GB Gigabit Ethernet Controller.
14. Legacy Transmit Descriptor Write-Back May Occur Before the Packet Data
Associated with the Descriptor is Fetched
Problem:
Implication:
Workaround:
Status:
If a legacy transmit operation directly follows a TCP Segmentation Offload transmit operation, the logic may
incorrectly associate the successful completion of the TSO transmit with the next descriptor. If the next
descriptor is a legacy descriptor, under certain timing scenarios it is possible for the legacy descriptor to be
incorrectly written back to host memory with the DD bit set. This might occur even though the packet data for
the legacy descriptor has not yet been fetched.
Due to the premature write back, an operating system may release and reallocate the transmit buffer, potentially
causing buffer re-use or transmission of incorrect data.
Utilize at least two descriptors for any legacy transmit operation. Do not reallocate any buffers associated with
the transmit operation until the last descriptor has been written back.
Intel does not plan to resolve this erratum in a future stepping of the 82546GB Gigabit Ethernet Controller.
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