82546GB Datasheet, PDF (12/16 Pages) Intel Corporation – Gigabit Ethernet Controller Specification Update

82546GB GIGABIT ETHERNET CONTROLLER SPECIFICATION UPDATE
10. Hang in PCI-X systems due to 2k Buffer Overrun during Transmit Operation
Problem:
Implication:
This Ethernet device has an error in the way that it stores data from PCI-X read transactions. If the controller is
operating in PCI-X mode and its read data FIFO fills completely then the device can miscalculate the amount of
free space in the FIFO and lose all of this data.
This erratum does not apply to devices running in PCI mode only.
If this device enters this erratum state, the chip loses 2 kilobytes of data. The transmit and receive units of the
chip will hang waiting for this data which will never arrive. No data will be corrupted. Once this has occurred, a
reset is required to restore the device to normal operation.
Workaround:
Status:
If using larger MTUs (jumbo frames), the chance of reaching this erratum state also increases.
The issue can occur only when one packet is being completed and the next being started. Therefore, if the first
fragment of every packet is limited in size the overflow can be prevented entirely. Drivers can work around this
issue by ensuring that the size in the first descriptor of every packet less than 2016 bytes.
Intel does not plan to resolve this erratum in a future stepping of the 82546GB Gigabit Ethernet Controller.
11. CRC Errors due to Rate Adaptation FIFO Overflow in Fiber Mode
Problem:
In TBI mode and internal-SERDES mode this Ethernet device uses a small FIFO in its receive path to
compensate for minute differences between the speed of the link partner's clock and the device's local clock. If
the link partner has a faster clock, this FIFO will fill slowly during a packet, and then drain during inter-frame
gaps.
The device has an error in the way that this FIFO empties, causing it to wait several cycles into the inter-frame
gap before it begins recovering clock drift.
Implication:
This only occurs during operation in fiber mode. Internal PHY mode used for copper applications is unaffected
by this erratum.
If the Ethernet device is linked to a partner with a substantially faster clock and multiple frames arrive in
sequence with minimal inter-frame spacing, then the device may not have time to recover all of the accumulated
drift between frames. The synchronization FIFO will overflow and drop 4 bytes of the packet, which will be
visible as a CRC error.
Workaround:
The larger the difference between the link partner's clock and the Ethernet controller's clock, the fewer back-to-
back frames need to be received to see CRC errors. In practice, this will be a very rare occurrence for two
reasons. First, most Ethernet devices use clock frequencies near the center of the allowed range, so the
difference between clocks will be small. Second, long strings of packets with minimal inter-frame spacing are
rare on most networks.
This erratum may be worked around by setting a larger inter-frame spacing. Specifically, switches must be
configured to an inter-frame gap of at least 144 ns (18 symbols) for MTUs less than 10,000 bytes or at least 160
ns (20 symbols) for MTUs between 10,001 and 16,000 bytes.
Status:
Alternatively, a new board design could use a reference clock source with a frequency near the high end of the
802.3 standard's allowed range. This would create a situation where the only way to trigger the erratum was for
the link partner to have a faster clock which would violate the 802.3 standard.
Intel does not plan to resolve this erratum in a future stepping of the 82546GB Gigabit Ethernet Controller.
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