FW82801EB-SL73Z Datasheet, PDF (79/671 Pages) Intel Corporation – Intel® 82801EB I/O Controller Hub 5 (ICH5) / Intel® 82801ER I/O Controller Hub 5 R (ICH5R)

Functional Description
Functional Description
5
This chapter describes the functions and interfaces of the ICH5.
5.1
Hub Interface to PCI Bridge (D30:F0)
The hub interface to PCI bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the
ICH5 implements the buffering and control logic between PCI and the hub interface. The
arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must
decode the ranges for the hub interface. All register contents are lost when core well power is
removed.
5.1.1 PCI Bus Interface
The ICH5 PCI interface provides a 33 MHz, PCI Local Bus Specification, Revision 2.3-compliant
implementation. All PCI signals are 5 V tolerant (except PME#). The ICH5 integrates a PCI arbiter
that supports up to six external PCI bus masters in addition to the internal ICH5 requests.
Note that most transactions targeted to the ICH5 first appear on the external PCI bus before being
claimed back by the ICH5. The exceptions are I/O cycles involving USB, IDE, SATA, and AC ’97.
These transactions complete over the hub interface without appearing on the external PCI bus.
Configuration cycles targeting USB, IDE, SATA, or AC ’97 appear on the PCI bus. If the ICH5 is
programmed for positive decode, the ICH5 claims the cycles appearing on the external PCI bus in
medium decode time. If the ICH5 is programmed for subtractive decode, the ICH5 claims these
cycles in subtractive time. If the ICH5 is programmed for subtractive decode, these cycles can be
claimed by another positive decode agent out on PCI. This architecture enables the ability to boot
off of a PCI card that positively decodes the boot cycles. In order to boot off a PCI card it is
necessary to keep the ICH5 in subtractive decode mode. When booting off a PCI card, the
BOOT_STS bit (bit 2, TCO2 Status Register) will be set.
Note: The ICH5’s AC ’97, IDE and USB controllers cannot perform peer-to-peer traffic.
Note: PCI Bus Masters should not use memory area locations as a target if that area is programmed to
anything but Read/Write.
Note:
PCI configuration write cycles, initiated by the processor, with the following characteristics are
converted to a Special Cycle with the Shutdown message type.
• Device Number (AD[15:11]) = 11111
• Function Number (AD[10:8]) = 111
• Register Number (AD[7:2]) = 000000
• Data = 00h
• Bus number matches secondary bus number
Intel^® 82801EB ICH5 / 82801ER ICH5R Datasheet
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