FW82801EB-SL73Z Datasheet, PDF (404/671 Pages) Intel Corporation – Intel® 82801EB I/O Controller Hub 5 (ICH5) / Intel® 82801ER I/O Controller Hub 5 R (ICH5R)

LPC Interface Bridge Registers (D31:F0)
9.11.2
9.11.3
9.11.4
TCO_TMR—TCO Timer Initial Value Register
I/O Address:
Default Value:
Lockable:
TCOBASE +01h
04h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:6 Reserved
TCO Timer Initial Value — R/W. This field provides the value that is loaded into the timer each time
5:0
the TCO_RLD register is written. Values of 0h–3h are ignored and should not be attempted. The
timer is clocked at approximately 0.6 seconds, and this allows timeouts ranging from 2.4 seconds to
38 seconds.
TCO_DAT_IN—TCO Data In Register
I/O Address:
Default Value:
Lockable:
TCOBASE +02h
00h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
TCO Data In Value — R/W. This data register field is used for passing commands from the OS to
7:0 the SMI handler. Writes to this register will cause an SMI and set the SW_TCO_SMI bit in the
TCO1_STS register.
TCO_DAT_OUT—TCO Data Out Register
I/O Address:
Default Value:
Lockable:
TCOBASE +03h
00h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
TCO Data Out Value — R/W. This data register field is used for passing commands from the SMI
7:0 handler to the OS. Writes to this register will set the TCO_INT_STS bit in the TCO_STS register. It
will also cause an interrupt, as selected by the TCO_INT_SEL bits.
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Intel^® 82801EB ICH5 / 82801ER ICH5R Datasheet