FW82801EB-SL73Z Datasheet, PDF (12/671 Pages) Intel Corporation – Intel® 82801EB I/O Controller Hub 5 (ICH5) / Intel® 82801ER I/O Controller Hub 5 R (ICH5R)

Contents
5.21.2 Bus Arbitration ..................................................................................................... 243
5.21.3 Bus Timing........................................................................................................... 243
5.21.3.1 Clock Stretching................................................................................... 243
5.21.3.2 Bus Time Out (Intel^® ICH5 as SMBus Master) .................................... 243
5.21.4 Interrupts / SMI# .................................................................................................. 244
5.21.5 SMBALERT# ....................................................................................................... 245
5.21.6 SMBus CRC Generation and Checking............................................................... 245
5.21.7 SMBus Slave Interface ........................................................................................ 245
5.21.7.1 Format of Slave Write Cycle ................................................................ 246
5.21.7.2 Format of Read Command .................................................................. 248
5.21.7.3 Format of Host Notify Command ......................................................... 250
5.22 AC ’97 Controller (Audio D31:F5, Modem D31:F6) .......................................................... 251
5.22.1 PCI Power Management...................................................................................... 253
5.22.2 AC-Link Overview ................................................................................................ 253
5.22.2.1 AC-Link Output Frame (SDOUT) ......................................................... 256
5.22.2.2 Output Slot 0: Tag Phase..................................................................... 256
5.22.2.3 Output Slot 1: Command Address Port................................................ 256
5.22.2.4 Output Slot 2: Command Data Port ..................................................... 257
5.22.2.5 Output Slot 3: PCM Playback Left Channel ......................................... 257
5.22.2.6 Output Slot 4: PCM Playback Right Channel....................................... 257
5.22.2.7 Output Slot 5: Modem Codec............................................................... 257
5.22.2.8 Output Slot 6: PCM Playback Center Front Channel........................... 257
5.22.2.9 Output Slots 7–8: PCM Playback Left
and Right Rear Channels..................................................................... 257
5.22.2.10 Output Slot 9: Playback Sub Woofer Channel ..................................... 258
5.22.2.11 Output Slots 10–11: Reserved............................................................. 258
5.22.2.12 Output Slot 12: I/O Control................................................................... 258
5.22.2.13 AC-Link Input Frame (SDIN)................................................................ 258
5.22.2.14 Input Slot 0: Tag Phase ....................................................................... 259
5.22.2.15 Input Slot 1: Status Address Port / Slot Request Bits .......................... 259
5.22.2.16 Input Slot 2: Status Data Port .............................................................. 260
5.22.2.17 Input Slot 3: PCM Record Left Channel............................................... 260
5.22.2.18 Input Slot 4: PCM Record Right Channel ............................................ 260
5.22.2.19 Input Slot 5: Modem Line ..................................................................... 260
5.22.2.20 Input Slot 6: Optional Dedicated Microphone
Record Data......................................................................................... 261
5.22.2.21 Input Slots 7–11: Reserved.................................................................. 261
5.22.2.22 Input Slot 12: I/O Status....................................................................... 261
5.22.2.23 Register Access ................................................................................... 261
5.22.3 AC-Link Low Power Mode ................................................................................... 262
5.22.3.1 External Wake Event ........................................................................... 263
5.22.4 AC ’97 Cold Reset ............................................................................................... 264
5.22.5 AC ’97 Warm Reset ............................................................................................. 264
5.22.6 System Reset ...................................................................................................... 264
5.22.7 Hardware Assist to Determine AC_SDIN Used Per Codec ................................. 265
5.22.8 Software Mapping of AC_SDIN to DMA Engine .................................................. 265
6 Register and Memory Mapping ................................................................................................ 267
6.1 PCI Devices and Functions .............................................................................................. 268
6.2 PCI Configuration Map ..................................................................................................... 269
6.3 I/O Map ............................................................................................................................. 269
6.3.1 Fixed I/O Address Ranges................................................................................... 269
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Intel^® 82801EB ICH5 / 82801ER ICH5R Datasheet