FW82801EB-SL73Z Datasheet, PDF (216/671 Pages) Intel Corporation – Intel® 82801EB I/O Controller Hub 5 (ICH5) / Intel® 82801ER I/O Controller Hub 5 R (ICH5R)

Functional Description
5.20.1.3
5.20.1.4
Driver Initialization
See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal Serial Bus,
Revision 1.0.
EHC Resets
In addition to the standard ICH5 hardware resets, portions of the EHC are reset by the HCRESET
bit and the transition from the D3hot device power management state to the D0 state. The effects of
each of these resets are:
Reset
HCRESET bit set.
Does Reset
Does not Reset
Memory space registers
except Structural
Parameters (which is
written by BIOS).
Configuration
registers.
Software writes the
Device Power State
from D3hot (11b) to
D0 (00b).
Core well registers
(except BIOS-
programmed registers).
Suspend well
registers; BIOS-
programmed core
well registers.
Comments
The HCRESET must only affect
registers that the EHCI driver
controls. PCI Configuration space
and BIOS-programmed parameters
can not be reset.
The D3-to-D0 transition must not
cause wake information (suspend
well) to be lost. It also must not clear
BIOS-programmed registers
because BIOS may not be invoked
following the D3-to-D0 transition.
If the detailed register descriptions give exceptions to these rules, those exceptions override these
rules. This summary is provided to help explain the reasons for the reset policies.
5.20.2
Data Structures in Main Memory
See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification for
Universal Serial Bus, Revision 1.0 for details.
5.20.3
5.20.3.1
USB 2.0 Enhanced Host Controller DMA
The ICH5 USB 2.0 EHC implements three sources of USB packets. They are, in order of priority
on USB during each microframe, 1) the USB 2.0 Debug Port (see Section USB 2.0 Based Debug
Port), 2) the Periodic DMA engine, and 3) the Asynchronous DMA engine. The ICH5 always
performs any currently-pending debug port transaction at the beginning of a microframe, followed
by any pending periodic traffic for the current microframe. If there is time left in the microframe,
then the EHC performs any pending asynchronous traffic until the end of the microframe (EOF1).
Note that the debug port traffic is only presented on one port (Port #0), while the other ports are
idle during this time.
The following subsections describe the policies of the periodic and asynchronous DMA engines.
Periodic List Execution
The Periodic DMA engine contains buffering for two control structures (two transactions). By
implementing two entries, the EHC is able to pipeline the memory accesses for the next transaction
while executing the current transaction on the USB ports. Note that a multiple-packet,
High-Bandwidth transaction occupies one of these buffer entries, which means that up to six, 1-KB
data packets may be associated with the two buffered control structures.
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Intel^® 82801EB ICH5 / 82801ER ICH5R Datasheet