FW82801EB-SL73Z Datasheet, PDF (176/671 Pages) Intel Corporation – Intel® 82801EB I/O Controller Hub 5 (ICH5) / Intel® 82801ER I/O Controller Hub 5 R (ICH5R)

Functional Description
5.16.1.3 PIO IDE Timing Modes
IDE data port transaction latency consists of startup latency, cycle latency, and shutdown latency.
Startup latency is incurred when a PCI master cycle targeting the IDE data port is decoded and the
DA[2:0] and CSxx# lines are not set up. Startup latency provides the setup time for the DA[2:0]
and CSxx# lines prior to assertion of the read and write strobes (DIOR# and DIOW#).
Cycle latency consists of the I/O command strobe assertion length and recovery time. Recovery
time is provided so that transactions may occur back-to-back on the IDE interface (without
incurring startup and shutdown latency) without violating minimum cycle periods for the IDE
interface. The command strobe assertion width for the enhanced timing mode is selected by the
IDE_TIM Register and may be set to 2, 3, 4, or 5 PCI clocks. The recovery time is selected by the
IDE_TIM Register and may be set to 1, 2, 3, or 4 PCI clocks.
If IORDY is asserted when the initial sample point is reached, no wait-states are added to the
command strobe assertion length. If IORDY is negated when the initial sample point is reached,
additional wait-states are added. Since the rising edge of IORDY must be synchronized, at least
two additional PCI clocks are added.
Shutdown latency is incurred after outstanding scheduled IDE data port transactions (either a
non-empty write post buffer or an outstanding read prefetch cycles) have completed and before
other transactions can proceed. It provides hold time on the DA[2:0] and CSxx# lines with respect
to the read and write strobes (DIOR# and DIOW#). Shutdown latency is two PCI clocks in
duration.
The IDE timings for various transaction types are shown in Table 76. Note that bit 2 (16-bit I/O
recovery enable) of the ISA I/O Recovery Timer Register does not add wait-states to IDE data port
read accesses when any of the fast timing modes are enabled.
Table 76. IDE Transaction Timings (PCI Clocks)
IDE Transaction Type
Startup
Latency
Non-Data Port Compatible
4
Data Port Compatible
3
Fast Timing Mode
2
IORDY Sample
Point (ISP)
11
6
2–5
Recovery Time
(RCT)
22
14
1–4
Shutdown
Latency
2
2
2
5.16.1.4
IORDY Masking
The IORDY signal can be ignored and assumed asserted at the first IORDY Sample Point (ISP) on
a drive by drive basis via the IDETIM Register.
5.16.1.5
PIO 32-Bit IDE Data Port Accesses
A 32-bit PCI transaction run to the IDE data address (01F0h primary, 0170h secondary) results in
two back to back 16-bit transactions to the IDE data port. The 32-bit data port feature is enabled for
all timings, not just enhanced timing. For compatible timings, a shutdown and startup latency is
incurred between the two, 16-bit halves of the IDE transaction. This guarantees that the chip selects
are deasserted for at least two PCI clocks between the two cycles.
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Intel^® 82801EB ICH5 / 82801ER ICH5R Datasheet