FW82801EB-SL73Z Datasheet, PDF (530/671 Pages) Intel Corporation – Intel® 82801EB I/O Controller Hub 5 (ICH5) / Intel® 82801ER I/O Controller Hub 5 R (ICH5R)

SMBus Controller Registers (D31:F3)
14.2.16 SLV_CMD—Slave Command Register
(SMBUS—D31:F3)
Register Offset: 11h
Default Value:
00h
Attribute:
Size:
R/W
8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit
Description
7:2 Reserved
SMBALERT_DIS — R/W.
0 = Allows the generation of the interrupt or SMI#.
2
1 = Software sets this bit to block the generation of the interrupt or SMI# due to the SMBALERT#
source. This bit is logically inverted and ANDed with the SMBALERT_STS bit. The resulting
signal is distributed to the SMI# and/or interrupt generation logic. This bit does not effect the
wake logic.
HOST_NOTIFY_WKEN — R/W. Software sets this bit to 1 to enable the reception of a Host Notify
command as a wake event. When enabled this event is “OR”ed in with the other SMBus wake
1
events and is reflected in the SMB_WAK_STS bit of the General Purpose Event 0 Status register.
0 = Disable
1 = Enable
HOST_NOTIFY_INTREN — R/W. Software sets this bit to 1 to enable the generation of interrupt or
SMI# when HOST_NOTIFY_STS is 1. This enable does not affect the setting of the
HOST_NOTIFY_STS bit. When the interrupt is generated, either PIRQB# or SMI# is generated,
0
depending on the value of the SMB_SMI_EN bit (D31, F3, Off40h, B1). If the HOST_NOTIFY_STS
bit is set when this bit is written to a 1, then the interrupt (or SMI#) will be generated. The interrupt
(or SMI#) is logically generated by AND’ing the STS and INTREN bits.
0 = Disable
1 = Enable
14.2.17 NOTIFY_DADDR—Notify Device Address Register
(SMBUS—D31:F3)
Register Offset: 14h
Default Value:
00h
Attribute:
Size:
RO
8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit
Description
DEVICE_ADDRESS — RO. This field contains the 7-bit device address received during the Host
7:1 Notify protocol of the System Management Bus (SMBus) Specification, Version 2.0. Software should
only consider this field valid when the HOST_NOTIFY_STS bit is set to 1.
0 Reserved
530
Intel^® 82801EB ICH5 / 82801ER ICH5R Datasheet