FW82801EB-SL73Z Datasheet, PDF (474/671 Pages) Intel Corporation – Intel® 82801EB I/O Controller Hub 5 (ICH5) / Intel® 82801ER I/O Controller Hub 5 R (ICH5R)

UHCI Controllers Registers
12.2.2
USBSTS—USB Status Register
I/O Offset:
Default Value:
Base + (02–03h)
0020h
Attribute:
Size:
R/WC
16 bits
This register indicates pending interrupts and various states of the host controller. The status
resulting from a transaction on the serial bus is not indicated in this register.
Bit
Description
15:6 Reserved
HCHalted — R/WC.
5
0 = Software clears this bit by writing a 1 to it.
1 = The host controller has stopped executing as a result of the Run/Stop bit being set to 0, either
by software or by the host controller hardware (debug mode or an internal error). Default.
Host Controller Process Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The host controller has detected a fatal error. This indicates that the host controller suffered a
4
consistency check failure while processing a Transfer Descriptor. An example of a consistency
check failure would be finding an illegal PID field while processing the packet header portion of
the TD. When this error occurs, the host controller clears the Run/Stop bit in the Command
register to prevent further schedule execution. A hardware interrupt is generated to the system.
Host System Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = A serious error occurred during a host system access involving the host controller module. In a
3
PCI system, conditions that set this bit to 1 include PCI Parity error, PCI Master Abort, and PCI
Target Abort. When this error occurs, the host controller clears the Run/Stop bit in the
Command register to prevent further execution of the scheduled TDs. A hardware interrupt is
generated to the system.
Resume Detect (RSM_DET) — R/WC.
2
0 = Software clears this bit by writing a 1 to it.
1 = The host controller received a “RESUME” signal from a USB device. This is only valid if the
Host controller is in a global suspend state (bit 3 of Command register = 1).
USB Error Interrupt — R/WC.
0 = Software clears this bit by writing a 1 to it.
1
1 = Completion of a USB transaction resulted in an error condition (e.g., error counter underflow). If
the TD on which the error interrupt occurred also had its IOC bit set, both this bit and Bit 0 are
set.
USB Interrupt (USBINT) — R/WC.
0 = Software clears this bit by writing a 1 to it.
0
1 = The host controller sets this bit when the cause of an interrupt is a completion of a USB
transaction whose Transfer Descriptor had its IOC bit set. Also set when a short packet is
detected (actual length field in TD is less than maximum length field in TD), and short packet
detection is enabled in that TD.
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Intel^® 82801EB ICH5 / 82801ER ICH5R Datasheet