82562EZ_08 Datasheet, PDF (6/66 Pages) Intel Corporation – Dual Footprint

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
4.1.11 Traces for Decoupling Capacitors ................................................................................. 26
4.1.12 Ground Planes Under the Magnetics Module................................................................ 26
4.1.13 Special Considerations for Non-Integrated
Magnetics Modules and RJ-45 Connectors................................................................... 28
4.2 Layout for the 82562EZ(EX) Platform LAN Connect Device ...................................................... 29
4.2.1 Termination Resistors for Designs Based on 82562EZ(EX) PLC Device...................... 29
4.2.2 Light Emitting Diodes for Designs Based on 82562EZ(EX) PLC Device....................... 29
4.3 Layout for the 82547GI(EI) Gigabit Ethernet Controller ............................................................. 30
4.3.1 Termination Resistors for Designs Based on 82547GI(EI) Gigabit Ethernet Controller 30
4.3.2 Light Emitting Diodes for Designs Based on 82547GI(EI) Controller ............................ 30
4.4 Physical Layer Conformance Testing ......................................................................................... 30
4.5 Troubleshooting Common Physical Layout Issues..................................................................... 31
5.0
Design and Layout Checklists.......................................................................................... 33
6.0
Ball Number to Signal Mapping with Population Options................................................. 35
7.0
Dual Footprint Reference Schematic ............................................................................... 43
A
Measuring LAN Reference Frequency Using a Frequency Counter................................ 51
B
GigConf.exe Register Settings for 82547GI(EI) Devices ................................................. 57
Figures
1
ICH5 Platform LAN Connect Sections .......................................................................................... 3
2
CSA Port Locally Generated Reference Divider Circuits.............................................................. 4
3
CSA port CI_RCOMP Circuits ...................................................................................................... 5
4
Crystal Circuit ............................................................................................................................... 9
5
LAN Disable Circuitry ................................................................................................................. 13
6
82547GI(EI) LAN Disable Circuitry ............................................................................................. 15
5
General Placement Distances .................................................................................................... 22
6
Trace Routing ............................................................................................................................. 23
7
Ground Plane Separation ........................................................................................................... 26
8
Ideal Ground Split Implementation ............................................................................................. 27
9
Termination Plane Example for 82562EZ(EX) PLC Device and Discrete Magnetics ................. 28
10 82562EZ(EX) PLC Device Differential Signal Termination......................................................... 29
11 Indirect Probing Setup ................................................................................................................ 52
12 Direct Probing Method ................................................................................................................ 55
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