82562EZ_08 Datasheet, PDF (21/66 Pages) Intel Corporation – Dual Footprint

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
3.3Vstb
Super IO
1K
GP Port
or
ICHx GPIO
24, 25, 27, 28
or
µController
(mobile)
3.3Vstb
Sensor/
Supervisor
RST#
3.3Vstb
470 Ω
MMBT3904
1K
100 Ω
100 Ω
100 Ω
100 Ω
TESTEN
ISOL_TCK
ISOL_TI
ISOL_TEX
LAN_RST#
RSMRST#
ICHx
Figure 5. LAN Disable Circuitry
Note: The 100 Ω resistors for the Test Mode signals are required for the Exclusive OR (XOR) Tree and
Isolate Mode.
3.2.2
Serial EEPROM for 82562EZ(EX) Implementations
Serial EEPROM for LAN implementations based on 82562EZ(EX) devices connects to the ICH5.
Depending upon the size of the EEPROM, the 82562EZ(EX) may or may not support legacy
manageability. Table 7 and Table 8 list the EEPROM map for the 82562EZ(EX) PLC device. For
details on the EEPROM, refer to the appropriate I/O Control Hub 2, 3, 4, 5, 6, and 7 EEPROM
Map and Programming Information.
Table 7. 82562EZ(EX) Memory Layout (128 Byte EEPROM)
00h
HW/SW Reserved Area
3Fh
NOTE: No manageability provided.
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