82562EZ_08 Datasheet, PDF (30/66 Pages) Intel Corporation – Dual Footprint

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
Keep silicon traces at least 1 inch from
edge of PCB (2 inches preferred)
Keep LAN silicon 1 to 4 inches from LAN connector
Integrated
RJ-45
w/LAN
Magnetics
LAN
Silicon
Keep 100 mil minimum distance between TX
and RX traces (300 mils is preferred)
Figure 5. General Placement Distances
Figure 5 shows some basic placement distance guidelines. The figure shows two differential pairs,
but can be generalized for a Gigabit system with four analog pairs. The ideal placement for the
Ethernet silicon would be approximately one inch behind the magnetics module.
While it is generally a good idea to minimize lengths and distances, this figure also illustrates the
need to keep the LAN silicon away from the edge of the board and the magnetics module for best
EMI performance.
4.1.2
Crystals
Crystals should not be placed near I/O ports or board edges. Radiation from these devices may be
coupled onto the I/O ports or out of the system chassis. Crystals should also be kept away from the
Ethernet magnetics module to prevent interference. Traces should be referenced to a continuous
low impedance plane.
Place the crystal and load capacitors on the printed circuit boards as close to the Ethernet
component as possible, within 0.75 inch. Keep other potentially noisy traces away from the crystal
traces.
4.1.3
Board Stack Up Recommendations
Printed circuit boards for these designs typically have four, six, eight, or more layers. Here is a
description of a typical six-layer board stackup:
• Layer 1 is a signal layer. It can contain the differential analog pairs from the Ethernet device to
the magnetics module.
• Layer 2 is a signal ground layer. Chassis ground may also be fabricated in Layer 2 under the
connector side of the magnetics module.
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