82562EZ_08 Datasheet, PDF (34/66 Pages) Intel Corporation – Dual Footprint

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
4.1.11
4.1.12
The following guidelines help reduce circuit inductance in both backplanes and motherboards:
• Route traces over a continuous plane with no interruptions. Do not route over a split power or
ground plane. If there are vacant areas on a ground or power plane, avoid routing signals over
the vacant area. This will increase inductance and EMI radiation levels.
• Separate noisy digital grounds from analog grounds to reduce coupling. Noisy digital grounds
may affect sensitive DC subsystems.
• All ground vias should be connected to every ground plane; and every power via should be
connected to all power planes at equal potential. This helps reduce circuit inductance.
• Physically locate grounds between a signal path and its return. This will minimize the loop
area.
• Avoid fast rise/fall times as much as possible. Signals with fast rise and fall times contain
many high frequency harmonics, which can radiate EMI.
• The ground plane beneath the magnetics module should be split. The RJ-45 connector side of
the transformer module should have chassis ground beneath it. Split Ground Planes for
Magnetics Modules
Traces for Decoupling Capacitors
Traces between decoupling and I/O filter capacitors should be as short and wide as practical. Long
and thin traces are more inductive and would reduce the intended effect of decoupling capacitors.
Also for similar reasons, traces to I/O signals and signal terminations should be as short as
possible. Vias to the decoupling capacitors should be sufficiently large in diameter to decrease
series inductance.
Ground Planes Under the Magnetics Module
The magnetics module chassis or output ground (secondary side of transformer) should be
separated from the digital or input ground (primary side) by a physical separation of 100 mils
minimum. Splitting the ground planes beneath the transformer minimizes noise coupling between
the primary and secondary sides of the transformer and between the adjacent coils in the magnetics.
This arrangement also improves the common mode choke functionality of magnetics module.
Table 7 illustrates the split plane layout for a discrete magnetics module. Capacitors are used to
interconnect chassis ground and signal ground.
.
0.10 Inches Minimum Spacing
Magnetics Module
Figure 7. Ground Plane Separation
Void or Separate
Ground Plane
Separate Chassis Ground Plane
Gnd_Plane_Sep
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