82562EZ_08 Datasheet, PDF (32/66 Pages) Intel Corporation – Dual Footprint

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
• The reference plane for the differential pairs should be continuous and low impedance. It is
recommended that the reference plane be either ground or 1.8 V (the voltage used by the
PHY). This provides an adequate return path for and high frequency noise currents.
• Do not route differential pairs over splits in the associated reference plane.
• Differential termination components should be placed as close as possible to the LAN silicon.
4.1.5
Signal Trace Geometry
The key factors in controlling trace EMI radiation are the trace length and the ratio of trace-width
to trace-height above the ground plane. To minimize trace inductance, high-speed signals and
signal layers that are close to a ground or power plane should be as short and wide as practical.
Ideally, this trace width to height above the ground plane ratio is between 1:1 and 3:1. To maintain
trace impedance, the width of the trace should be modified when changing from one board layer to
another if the two layers are not equidistant from the power or ground plane.
Each pair of signal should have a differential impedance of 100 Ω. +/- 20%. If a particular tool
cannot design differential traces, it is permissible to specify 55-65 Ω single-ended traces as long as
the spacing between the two traces is minimized. As an example, consider a differential trace pair
on Layer 1 that is eight mils (0.2 mm) wide and two mils (0.05 mm) thick, with a spacing of eight
mils (0.2mm). If the fiberglass layer is eight mils (0.2 mm) thick with a dielectric constant, E_R, of
4.7, the calculated single-ended impedance would be approximately 61 Ω and the calculated
differential impedance would be approximately 100 Ω.
When performing a board layout, do not allow the CAD tool auto-router to route the differential
pairs without intervention. In most cases, the differential pairs will have to be routed manually. The
components should be laid out in the following order of priority:
1. Differential traces
2. Termination resistors
3. Bypass capacitors
4. Other components
This allows placing those components in the best locations and avoids using critical space by non-
critical components.
Note:
Measuring trace impedance for layout designs targeting 100 Ω often results in lower actual
impedance. Designers should verify actual trace impedance and adjust the layout accordingly. If
the actual impedance is consistently low, a target of 105 to 110 Ω should compensate for second
order effects.
It is necessary to compensate for trace-to-trace edge coupling, which can lower the differential
impedance by up to 10 Ω, when the traces within a pair are closer than 30 mils (edge to edge).
4.1.6
Trace Length and Symmetry
As indicated earlier in Section 4.1.4, the overall length of differential pairs should be less than four
inches measured from the Ethernet device to the magnetics.
The differential traces should be equal within 50 mils (1.25 mm) within each pair and as
symmetrical as possible. Asymmetrical and unequal length traces in the differential pairs
contribute to common mode noise. Common mode noise can degrade the receive circuit’s
performance and contribute to radiated emissions.
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