82563EB Datasheet, PDF (39/52 Pages) Intel Corporation – Intel® 82563EB/82564EB Gigabit Ethernet Controllers

82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon
Table 33. Reset Specification
Title
PHY_PWR_GOOD pulse
T_ppg
T_xoc
T_pco
Description
Min
Minimum pulse width for
LAN_PWR_GOOD
100
Minimum time PHY_PWR_GOOD must be
low after power supply is in operating
100
range
Time from oscillator stable to
PHY_PWR_GOOD assertion, when using 100
an external oscillator.
Time from PHY_PWR_GOOD assertion
until the 82563EB/82564EB outputs the
-
PHY_CLK_OUT.
Max Units
-
µs
-
µs
-
µs
350
µs
There are no required timing relationships between PHY_RESET_N, PHY_SLEEP, and either
PHY_PWR_GOOD, the power supply being stable, or the oscillator being stable. The 82563EB/
82564EB will come out of reset when both PHY_PWR_GOOD is asserted (1b) and
PHY_RESET_N is deasserted (1b). It will be active when PHY_PWR_GOOD is asserted (1b),
PHY_RESET_N is deasserted (1b), and PHY_SLEEP is deasserted (0b).
4.9
Power Consumption
The 82563EB/825654EB’s power consumption (Tables 34 through 37) is the sum of each port’s
power consumption. A port’s power consumption depends on whether the port’s logic, PHY, and
Kumeran are operational, and the 82563EB/825654EB’s operating speeds. These in turn, depend
on the following factors:
PHY_PWR_GOOD input
Powers off the entire chip (including PHY_CLK_OUT) when 0b. It has priority
over PHY_RESET_N or PHY_SLEEP.
PHY_RESET_N input When 0b, the entire chip is held in reset except PHY_CLK_OUT.
PHY_SLEEP input When 1b the entire chip is powered down, except PHY_CLK_OUT.
Port Disable Register
The port’s PHY and Kumeran can be disabled by writing a 1b to the “Disable
Port” bit of the “Power Management Control” register.
PHY Power Down
ThE 82563EB/82564EB can be powered down with an indication over the
Kumeran bus or by writing a 1b to the “Control Register’s” “Power Down” bit.
Link Down
When the link is required but the link is down the 82563EB/82564EB remains
in energy detect mode, attempting to detect energy from the link partner.
Speed
The 82563EB/82564EB uses progressively more power as the speed
increases from 10 Mb/s to 100 Mb/s to 1000 Mb/s. Speed is normally based on
auto-negotiation with the link partner, but may be forced or influenced by the
power state.
Power State
The power state can be used in conjunction with the “Low Power Link Up” and
“Auto-Negotiation 1000 Disable” to control the 82563EB/82564EB’s speed.
Kumeran Electrical Idle Nothing is transmitted on the differential pairs.
33