82563EB Datasheet, PDF (28/52 Pages) Intel Corporation – Intel® 82563EB/82564EB Gigabit Ethernet Controllers

82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon
Table 21. 3.3V External Power Supply Parameters
Title
Description
Min
Max
Ripple
Maximum voltage ripple (peak to
peak)^a
-
100
Overshoot
Maximum overshoot allowed
-
660
Maximum overshoot allowed
duration.
Overshoot Settling
Time
(At that time delta voltage should be
-
3
lower than 5 mV from steady state
voltage)
a. The peak to peak output ripple is measured at 20 MHz Bandwidth within the operational range.
Units
mV
mV
ms
4.4.4
Internal LVR Power Sequencing
All supplies should rise monotonically. Sequencing of the supplies is controlled by the 82563EB/
82564EB.
4.4.4.1
Power up Sequencing and Tracking
During power up, the sequencing and tracking of the internally controlled supplies (1.9V and 1.2V)
is controlled by the 82563EB/82564EB. No specific motherboard requirements are necessary to
prevent electrical overstress or latch-up.
• The 82563EB/82564EB analog voltage (1.9V) will never exceed the 3.3V supply at any time
during the power up. This is because the 1.9V supply is generated from the 3.3V supply when
using the internal voltage regulator control logic (see Figure 5 and Figure 6 for a schematic of
the internal LVR circuit). The 1.9V supply will track the 3.3V ramp.
• The 82563EB/82564EB core voltage (1.2V) will never exceed the 3.3V at any time during the
power up. This is because the 1.2V supply is generated from the 3.3V supply when using the
internal voltage regulator control logic (see Figure 5 and Figure 6 for a schematic of the
internal LVR circuit). The 1.2V ramp is delayed internally to prevent it from exceeding the
1.9V and 3.3V supply at any time. The delay is proportional to the slope of the 3.3V ramp.
The delay is approximated by T_ramp(3.3V)*0.25 < T_delay(1.2V) < T_ramp(3.3V)*0.75. T_ramp is
defined to the ramp rate of the 3.3V input to the internal voltage regulator circuit.
22