82563EB Datasheet, PDF (12/52 Pages) Intel Corporation – Intel® 82563EB/82564EB Gigabit Ethernet Controllers

82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon
3.2
Shared PHY Pins
Table 1. Shared PHY Pins
Signal Name
PHY_REF
Pin
Type
Sub-
Type
Description
50 B
PHY Reference
B
External 4.99 KΩ ± 1% resistor connection to VSS.
3.3
MDIO Interface
Table 2. MDIO Interface Pins
Note: For normal operation, the MDIO interface is strapped externally according to Table 39 due to
MDIO being an in-band operation.
Signal Name
Pin
Type
Sub-
Type
Description
MDC
MDIO
MDIO_ADD[0]
MDIO_ADD[1]
MDIO_ADD[2]
MDIO_ADD[3]
77 I (T) TTL
Management Data Clock
This signal is received from the 631xESB/632xESB as a clock
timing reference for information transfer on the MDIO signal. It is
not required to be a continuous signal and can be frozen when
no management data is transferred. This signal has a maximum
operating frequency of 2.5 MHz.
A 1 - 10 KΩ ± 5% pull-down resistor should be connected to this
pin.
76
I/O
PU
TTL6
Management Data Input/Output
Bi-directional data signal of the management data interface.
This pin has an internal pull-up. This signal can be left
disconnected (or pulled up) if not used.
78
79
I (T) TTL
18
19
Bits 4:1 of MDIO address
These bits are latched at the assertion of PHY_PWR_GOOD or
the de-assertion of PHY_RESET_N or PHY_SLEEP. They set
the MDIO address as follows:
• bit 1 = MDIO_ADD[0]
• bit 2 = MDIO_ADD[1]
• bit 3 = MDIO_ADD[2]
• bit 4 = MDIO_ADD[3]
A 1 -10 kΩ ± 5% pull-down resistor should be connected to each
of these pins.
6