82563EB Datasheet, PDF (17/52 Pages) Intel Corporation – Intel® 82563EB/82564EB Gigabit Ethernet Controllers

82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon
3.11
Clock Generator Interface
Table 10. Clock Generator Related Signals
Signal Name
Pin Type
Sub-
Type
Description
XTAL1
XTAL2
21 I
TTL
20 A-o A
PHY_CLK_OUT 96 O
TTL8
25 MHz Clock/Crystal Input
25 MHz +/- 50 ppm input. Can be connected to an oscillator or a
crystal. If using a crystal, XTAL2 must be connected as well. If a
crystal is used, it must be placed within ½-inch of the XTAL1 and
XTAL2 chip pins.
25 MHz Crystal Output
Output of internal oscillator circuit used to drive crystal into
oscillation. If using an oscillator, XTAL2 is left as a no connect.
Clock Output
Output clock available for use by a 631xESB/632xESB or other
component(s).
The speed depends on the how LINK_A is sampled at
LAN_PWR_GOOD assertion:
If LINK_A is 0b, the clock speed is 62.5 MHz.
If LINK_A is 1b, the clock speed is 25 MHz.
The output clock can be disabled depending on how LINK_B is
sampled at LAN_PWR_GOOD assertion:
If LINK_B is 0b: Clock output enabled (pulled-down).
If LINK_B is 1b: Clock output disabled (no connect).
3.12
Power/Ground Pins
Table 11. Power/Ground Pins (Sheet 1 of 2)
Signal Name
VSS
VSS
VDDO
Pin
Type
Sub-
Type
Description
Ground Exposed-Pad*
Central
Pad
G
G
The ground is provided through a large central pad on the
bottom side of the package.
89
G
G
Ground
11
22
60
P
P
3.3V I/O Ring Power
75
97
11