82563EB Datasheet, PDF (15/52 Pages) Intel Corporation – Intel® 82563EB/82564EB Gigabit Ethernet Controllers

82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon
3.7
Reset, Power Down, and Initialization Signals
Table 6. Reset and Power Down Signals
Signal Name
Pin
Type
Sub-
Type
Description
PHY_PWR_GOOD 83
PHY_RESET_N
81
PHY_SLEEP
80
TEST_JTAG
95
I
TTL
I
TTL
I (T) TTL
I PU TTL
Power Good (Power-On Reset)
The PHY_PWR_GOOD signal indicates good power is
available for The device. When set to 0b, the entire chip will be
held in a reset state.
Reset
When set to 0b, resets the device, including PHY and Kumeran
logic. Needs an external pull-up resistor if the signal isn’t
continuously being driven from an external source.
Sleep / Power Down
This will power down the PHY and the Kumeran of both ports.
Needs an external pull-down resistor, if the signal isn’t
continuously being driven from an external source.
Enable JTAG Pin Control
This pin should be pulled high through a 1 to 10 KΩ 5% resistor
in normal operation.
3.8
JTAG and IEEE Interface
Table 7. JTAG Signals
Signal Name
Pin
Type
Sub-
Type
Description
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
100 I
JTAG Clock
TTL _{This pin should be pulled high through a 1 to 10 KΩ 5% resistor}
in normal operation.
JTAG Serial Data Input
1
I PU TTL _{If not using JTAG, this pin may be pulled high through a 1 to}
10 KΩ 5% resistor
99 O
TTL3 JTAG Serial Data Output
JTAG TMS Input
3
I PU TTL _{If not using JTAG, this pin may be pulled high through a 1 to}
10 KΩ 5% resistor
9