82562GT Datasheet, PDF (35/46 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect (PLC)

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Networking Silicon — 82562GT
82562GT Test Port Functionality
The 82562GT’s XOR Tree Test Access Port (TAP) is the access point for test data to and from the
device. The port provides the ability to perform basic production level testing.
Asynchronous Test Mode
An asynchronous test mode is supported for system level design use. The modes are selected
through the use of the Test Port input pins (TESTEN, ISOL_TCK, ISOL_TI and ISOL_EXEC) in
static combinations. During normal operation the test pins must be pulled down through a resistor
(pulling Test high enables the test mode). All other port inputs may have a pull-down at the
designers discretion.
Test Function Description
The 82562GT TAP mode supports several tests that can be used in board level design. These tests
can help verify basic functionality and test the integrity of solder connections on the board. The
tests are described in the following sections.
The XOR Tree test mode is the most useful of the asynchronous test modes. It enables the
placement of the 82562GT to be validated at board test. The XOR Tree was chosen for its speed
advantages. Modern Automated Test Equipment (ATE) can perform a complete peripheral scan
without support at the board level. This command connects all output signals of the input buffers in
the device periphery into an XOR Tree scheme. All output drivers of the output-buffers, except the
test output (TOUT) pin, are put into high-Z mode. These pins are driven to affect the tree’s output.
Any hard strapped pins will prevent the tester from scanning correctly. The XOR Tree test mode is
obtained by placing the test pins in the following configuration (refer to Table 8):
TESTEN = 1
ISOL_TCK = 0
ISOL_TI = 0
ISOL_EXEC = 0.
Table 8. XOR Tree Chain Order
Chain Order
1
2
3
4
5
6
7
8
9
10
Chain
JTXD2
JTXD1
JTXD0
JRSTSYNC
ADV10 (LAN_DISABLE#)
JCLK
JRXD2
JRXD1
JRXD0
ACTLED#
Datasheet
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