82562GT Datasheet, PDF (17/46 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect (PLC)

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Networking Silicon — 82562GT
LED Pins
Pin Name
LILED#
ACTLED#
SPDLED#
Type
O
O
O
Description
Link Integrity LED. The LILED# signal has three logic modes. The LED
configurations are listed in Table 2, “LED Logic Functionality”.
Activity LED. The LED is active low and the Activity LED signal indicates either
receive or transmit activity. When no activity is present, the LED is off. The Activity
LED will flicker when activity is present. The flicker rate depends on the activity load.
If Address Matching mode is enabled by the MAC, this pin will also indicate address
match events on previously received frames.
Speed LED. The SPDLED# signal has three logic modes. The LED configurations
are listed in Table 2, “LED Logic Functionality”.
Miscellaneous Control Pins
Pin Name
Type
Description
ADV10/
I
LAN_DISABLE#
ISOL_TCK
I
ISOL_TI
I
ISOL_EXEC
I
TOUT
O
TESTEN
I
Advertise 10 Mbps Only. The Advertise 10 Mbps Only signal is asserted high,
and the 82562GT advertises only 10BASE-T technology during Auto-Negotiation
processes in this state. Otherwise, the 82562GT advertises all of its technologies.
Note: ADV10 has an internal 10 K Ω pull-down resistor.
LAN Disable in 82562G Mode. In the 82562G operating mode, this pin is used
as a LAN disable signal. When it is driven low, the device is fully powered down.
Test Clock. The Test Clock signal sets the device into asynchronous test mode
in conjunction with the Test Input, Test Execute and Test Enable pins (refer to
Table 1, “82562GT Hardware Configuration”).
In the manufacturing test mode, it acts as the test clock.
Note: ISOL_TCK has an internal 10 K Ω pull-down resistor.
Test Input. The Test Input signal sets the device into asynchronous test mode in
conjunction with the Test Clock, Test Execute and Test Enable pins (refer to
Table 1, “82562GT Hardware Configuration”).
In the manufacturing test mode, it acts as the test data input pin.
Note: ISOL_TI has an internal 10 K Ω pull-down resistor.
Test Execute. The Test Execute signal sets the device into asynchronous test
mode in conjunction with the Test Clock, Test Input, and Test Enable pins (refer to
Table 1, “82562GT Hardware Configuration”).
In the manufacturing test mode, it places the command that was entered through
the TI pin in the instruction register.
Note: ISOL_EXEC has an internal 10 K Ω pull-down resistor.
Test Output. The Test Output pin is used for Boundary XOR scan output. In the
manufacturing test mode, it acts as the test output port.
Test Enable. The Test Enable pin is used to enable test mode and should be
externally pulled up to V_CC to enable XOR Tree test mode.
Datasheet
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