82562GT Datasheet, PDF (16/46 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect (PLC)

82562GT — Networking Silicon
4.4
4.5
Clock Pins
Pin Name
X1
X2
Pin
Number
Type
46
I
47
O
Description
Crystal Input Clock. X1 and X2 can be driven by an external 25 MHz
crystal of 30 PPM. Otherwise, X1 is driven by an external metal-oxide
semiconductor (MOS) level 25 MHz oscillator when X2 is left floating.
Crystal Output Clock. X1 and X2 can be driven by an external 25 MHz
crystal of 30 PPM.
Platform LAN Connect Interface Pins
Pin Name
JCLK
JRSTSYNC
JTXD[2:0]
JRXD[2:0]
Pin
Number
Type
39
O
42
I
45, 44, I
43
37, 35, O
34
Description
LAN Connect Clock. The LAN Connect Clock is driven by the 82562GT
on two frequencies depending on operation speed. When the 82562GT is
in 100BASE-TX mode, JCLK drives a 50 MHz clock. Otherwise, JCLK
drives a 5 MHz clock for 10BASE-T. The JCLK does not stop during
normal operation.
Reset/Synchronize. This is a multiplexed pin and is driven by the Media
Access Control (MAC) layer device. Its functions are:
• Reset. When this pin is asserted beyond one LAN Connect clock
period, the 82562GT uses this signal Reset. To ensure reset of the
82562GT, the Reset signal should remain active for at least 500 µs.
• Synchronize. When this pin is activated synchronously, for only one
LAN Connect clock period, it is used to synchronize the MAC and
PHY on LAN Connect word boundaries.
LAN Connect Transmit Data. The LAN Connect transmit pins are used
to transfer data from the MAC device to the 82562GT. These pins are
used to move transmitted data and real time control and management
data. They also transmit out of band control data from the MAC to the
PHY. The pins should be fully synchronous to JCLK.
LAN Connect Receive Data. The LAN Connect receive pins are used to
transfer data from the 82562GT to the MAC device. These pins are used
to move received data and real time control and management data. They
also move out of band control data from the PHY to the MAC. These pins
are synchronous to JCLK.
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Datasheet