82562GT Datasheet, PDF (33/46 Pages) Intel Corporation – 10/100 Mbps Platform LAN Connect (PLC)

Networking Silicon — 82562GT
6.3.11
6.3.12
Register 27: PHY Unit Special Control Bit Definitions
Bit(s)
Name
15:6 Reserved
5
Switch Probe
Mapping
4
New mode
3
100BASE-TX
Receive Jabber
Disable
2:0
LED Switch
Control
Description
These bits are reserved and should be set to a
constant 0.
This bit switches the mapping on the LEDs. The LED
mapping is described below in bits 2:0, LED Switch
Control. This bit should always be set to 0b.
If this bit equals 0, the device is in 82562EZ (or
82562ET) mode.
If this bit equals 1, the device is in 82562GT (or
82562GZ) mode.
This bit enables the carrier sense disconnection while
the PHY is in jabber mode at 100 Mbps speed.
Value
000
001
010
011
100
101
110
111
ACTLED#
Activity
Speed
Speed
Activity
Off
Off
On
On
LILED#
Link
Collision
Link
Collision
Off
On
Off
On
Default
0
R/W
RO
0
RW
RO
0
RW
000 RW
Register 28: MDI/MDI-X Control Bit Definitions
Bit(s)
Name
15:8 Reserved
7
Auto Switch
Enable
6
Switch
Description
These bits are reserved and should be set to a
constant 0.
Enables the MDI/MDI-X feature (writing to this bit
overwrites the default value).
1 = Enabled.
0 = Disabled.
Manual switch (valid only if bit 7 is set to 0).
1 = Forces the port to be MDI-X (cross-over).
0 = Forces the port to be MDI (straight-through).
Default
0
R/W
RW
0
RW
RW
0
Datasheet
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