83C196EA Datasheet, PDF (16/40 Pages) Intel Corporation – CHMOS 16-BIT MICROCONTROLLER

83C196EA CHMOS 16-BIT MICROCONTROLLER — AUTOMOTIVE
Name
RPD
RXD1:0
SC1:0
SD1:0
T1CLK
T2CLK
Type
I
I/O
I/O
I/O
I
I
Table 4. Signal Descriptions (Continued)
Description
Return from Powerdown
Timing pin for the return-from-powerdown circuit.
If your application uses powerdown mode, connect a capacitor between RPD
and V_SS if either of the following conditions are true.
• the internal oscillator is the clock source
• the phase-locked loop (PLL) circuitry is enabled (see PLLEN signal
description)
The capacitor causes a delay that enables the oscillator and PLL circuitry to
stabilize before the internal CPU and peripheral clocks are enabled.
The capacitor is not required if your application uses powerdown mode and if
both of the following conditions are true.
• an external clock input is the clock source
• the phase-locked loop circuitry is disabled
If your application does not use powerdown mode, leave this pin unconnected.
RPD shares a package pin with P5.7.
Receive Serial Data 0 and 1
In modes 1, 2, and 3, RXD0 and 1 receive serial port input data. In mode 0, they
functions as either inputs or open-drain outputs for data.
RXD0 shares a package pin with P2.1 and RXD1 shares a package pin with
P2.4.
Clock Pins for SSIO0 and 1
For handshaking mode, configure SC1:0 as open-drain outputs.
This pin carries a signal only during receptions and transmissions. When the
SSIO port is idle, the pin remains either high (with handshaking) or low (without
handshaking).
SC0 shares a package pin with P10.0, and SC1 shares a package pin with
P10.2.
Data Pins for SSIO0 and 1
These pins are the data I/O pins for SSIO0 and 1.
SD0 shares a package pin with P10.1, and SD1 shares a package pin with
P10.1.
Timer 1 External Clock
External clock for timer 1.Timer 1 is programmable to increment or decement
on the rising edge, the falling edge, or both rising and falling edges of T1CLK.
and
External clock for the serial I/O baud-rate generator input (program selectable).
T1CLK shares a package pin with P7.0 and EPA0.
Timer 2 External Clock
External clock for timer 2. Timer 2 is programmable to increment or decement
on the rising edge, the falling edge, or both rising and falling edges of T2CLK.
T2CLK shares a package pin with P7.2 and EPA2.
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ADVANCE INFORMATION