83C196EA Datasheet, PDF (11/40 Pages) Intel Corporation – CHMOS 16-BIT MICROCONTROLLER

Name
AD15:0
ALE
ANGND
BHE#
BREQ#
83C196EA CHMOS 16-BIT MICROCONTROLLER — AUTOMOTIVE
Type
I/O
O
GND
O
O
Table 4. Signal Descriptions (Continued)
Description
Address/Data Lines
The function of these pins depend on the bus size and mode. When a bus
access is not occurring, these pins revert to their I/O port function.
16-bit Multiplexed Bus Mode:
AD15:0 drive address bits 0–15 during the first half of the bus cycle and drive or
receive data during the second half of the bus cycle.
8-bit Multiplexed Bus Mode:
AD15:8 drive address bits 8–15 during the entire bus cycle. AD7:0 drive
address bits 0–7 during the first half of the bus cycle and drive or receive data
during the second half of the bus cycle.
16-bit Demultiplexed Mode:
AD15:0 drive or receive data during the entire bus cycle.
8-bit Demultiplexed Mode:
AD7:0 drive or receive data during the entire bus cycle. AD15:8 drive the data
that is currently on the high byte of the internal bus.
Address Latch Enable
This active-high output signal is asserted only during external memory cycles.
ALE signals the start of an external bus cycle and indicates that valid address
information is available on the system address/data bus (A20:16 and AD15:0
for a multiplexed bus; A20:0 for a demultiplexed bus).
An external latch can use this signal to demultiplex address bits 0–15 from the
address/data bus in multiplexed mode.
ALE shares a package pin with P5.0.
Analog Ground
ANGND must be connected for A/D converter operation. ANGND and V_SS
should be nominally at the same potential.
Byte High Enable^†
During 16-bit bus cycles, this active-low output signal is asserted for word and
high-byte reads and writes to external memory. BHE# indicates that valid data
is being transferred over the upper half of the system data bus. Use BHE#, in
conjunction with AD0, to determine which memory byte is being transferred
over the system bus:
BHE# AD0 Byte(s) Accessed
0
0 both bytes
0
1 high byte only
1
0 low byte only
BHE# shares a package pin with P5.5 and WRH#.
† _{The chip configuration register 0 (CCR0) determines whether this pin func-}
tions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects
WRH#.
Bus Request
This active-low output signal is asserted during a hold cycle when the bus
controller has a pending external memory cycle.
You must enable the bus-hold protocol before using this signal.
BREQ# shares a package pin with P5.4.
ADVANCE INFORMATION
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