83C196EA Datasheet, PDF (15/40 Pages) Intel Corporation – CHMOS 16-BIT MICROCONTROLLER

Name
P10.5:0
P11.7:0
P12.4:0
PLLEN
PWM7:0
RD#
READY
RESET#
83C196EA CHMOS 16-BIT MICROCONTROLLER — AUTOMOTIVE
Type
I/O
I/O
I/O
I
O
O
I
I/O
Table 4. Signal Descriptions (Continued)
Description
Port 10
This is a standard, 6-bit, bidirectional port that is multiplexed with individually
selectable special-function signals.
Port 10 shares package pins with the following signals: P10.0/SC0, P10.1/SD0,
P10.2/SC1, P10.3/SD1, P10.4/EPA16, and P10.5.
Port 11
This is a standard, 8-bit, bidirectional port that is multiplexed with individually
selectable special-function signals.
P11.7:0 share package pins with PWM7:0.
Port 12
This is a memory-mapped, 5-bit, bidirectional port. P12.2:0 select the test-ROM
execution mode.
Phase-locked Loop Enable
This active-high input pin enables the on-chip clock doubler.
Pulse Width Modulator Outputs
These are PWM output pins with high-current drive capability.
PWM7:0 share package pins with P11.7:0.
Read
Read-signal output to external memory. RD# is asserted only during external
memory reads.
RD# shares a package pin with P5.3.
Ready Input
This active-high input signal is used to lengthen external memory cycles for
slow memory by generating wait states in addition to the wait states that are
generated internally.
When READY is high, CPU operation continues in a normal manner with wait
states inserted as programmed in the chip configuration registers or the chip-
select x bus control register. READY is ignored for all internal memory
accesses.
READY shares a package pin with P5.6.
Reset
A level-sensitive reset input to and open-drain system reset output from the
microcontroller. Either a falling edge on RESET# or an internal reset turns on a
pull-down transistor connected to the RESET# pin for 16 state times. In the
powerdown and idle modes, asserting RESET# causes the chip to reset and
return to normal operating mode. After a device reset, the first instruction fetch
is from FF2080H (or 1F2080H in external memory).
ADVANCE INFORMATION
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