IA82527_13 Datasheet, PDF (46/58 Pages) InnovASIC, Inc – Serial Communications Controller—CAN Protocol

IA82527
CAN Serial Communications Controller
Data Sheet
December 20, 2012
Table 16. Mode 3: Synchronous Operation Timing for 5.0V Operation
Symbol
1/t_XTAL
1/t_SCLK
1/t_MCLK
t_EHDV
t_ELDH
t_ELDZ
t_ELDV
t_AVEH
t_ELAV
t_CVEH
t_ELCV
t_DVEL
t_EHEL
t_AVAV
t_AVCL
t_CHAI
t_COPD
t_CHCL
Parameter
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
e High to Data Valid (for High-Speed Registers 02H,
04H, and 5H)
e High to Data Valid (for Low-Speed Registers) Read
Cycle without Previous Write^a
e High to Data Valid (for Low-Speed Registers) Read
Cycle with Previous Write
Data Hold after e Low for a Read Cycle
Data Float after e Low
Data Hold after e Low for a Write Cycle
Address and r-w_n to e Setup
Address and r-w_n Valid after e Falls
cs_n Valid to e High
cs_n Valid after e Low
Data Setup to e Low
e Active Width
Start of a Write Cycle after a Previous Write Access
Address or r-w_n to cs_n Low Setup
cs_n High Address Invalid
clkout Period (CD_V is the value loaded in the CLKOUT
Register representing the clkout divisor)
clkout High Period (CD_V is the value loaded in the
CLKOUT Register representing the clkout divisor)
Minimum
8 MHz
4 MHz
2 MHz
–
Maximum
16 MHz
10 MHz
8 MHz
55 ns
–
1.5 t_MCLK + 100
ns
–
3.5 t_MCLK + 100
ns
5 ns
–
–
35 ns
15 ns
–
25 ns
–
15 ns
–
0 ns
–
0 ns
–
55 ns
–
100 ns
–
2 t_MCLK
–
3 ns
–
7 ns
–
(CD_V + 1) × t_OSC
(CD_V + 1) × ½
t_OSC – 10
(CD_V + 1) × ½
t_OSC + 15
a_{A “Read Cycle without Previous Write” is where a read cycle follows a write cycle and where the falling}
edge of e for the write cycle and the rising edge of e for the read cycle are separated by at least 2 × t_MCLK.
IA211080504-07
Page 46 of 58
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