IA82527_13 Datasheet, PDF (40/58 Pages) InnovASIC, Inc – Serial Communications Controller—CAN Protocol

IA82527
CAN Serial Communications Controller
Data Sheet
December 20, 2012
Table 13. Mode 2: General Bus Timing for 3.3V Operation
Symbol Parameter
Minimum
Maximum
1/t_XTAL
1/t_SCLK
1/t_MCLK
t_AVSL
t_SLAX
t_ELDZ
t_EHDV
t_QVEL
t_ELQX
t_ELDV
t_EHEL
t_ELEL
t_SHSL
t_RSEH
t_SLEH
t_CLSL
t_ELCH
t_COPD
t_CHCL
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
Address Valid to as Low
Address Hold after as Low
Data Float after e Low
e High to Data Valid for Registers 02H, 04H, 05H
e High to Data Valid (all Registers except for 02H, 04H,
05H) for Read Cycle without a Previous Write^a
e High to Data Valid (all Registers except for 02H, 04H,
05H) for Read Cycle with a Previous Write
Data Setup to e Low
Input Data Hold after e Low
e Low to Output Data Valid on Port 1/2
e High Time
End of previous write (Last E Low) to E Low for Write
Cycle
as High Time
Setup Time of r-w_n to e High
as Low to e High
cs_n Low to as Low
e Low to cs_n High
clkout Period (CD_V is the value loaded in the CLKOUT
Register representing the clkout divisor)
clkout High Period (CD_V is the value loaded in the
CLKOUT Register representing the clkout divisor)
8 MHz
16 MHz
4 MHz
2 MHz
7.5 ns
10 ns
0 ns
0 ns
–
–
30 ns
20 ns
t_mclk
45 ns
10 MHz
8 MHz
–
–
45 ns
45 ns
1.5 t_mclk + 100
ns
3.5 t_mclk + 100
ns
–
–
2 t_mclk + 500 ns
2 t_mclk
30 ns
–
30 ns
–
20 ns
–
20 ns
–
0 ns
–
(CD_V + 1) × t_OSC
(CD_V + 1) × ½
t_OSC – 10
(CD_V + 1) × ½
t_OSC + 15
a_{A “Read Cycle without a Previous Write” is where a read cycle follows a write cycle and where}
the falling edge of e for the write and the rising edge of e for the read are separated by at least
2 × t_MCLK.
IA211080504-07
Page 40 of 58
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