IA82527_13 Datasheet, PDF (34/58 Pages) InnovASIC, Inc – Serial Communications Controller—CAN Protocol

IA82527
CAN Serial Communications Controller
Data Sheet
December 20, 2012
Table 10. Mode 0 and Mode 1: General Bus and Ready Timing for 5.0V Operation
Symbol
1/t_XTAL
1/t_SCLK
1/t_MCLK
t_AVLL
t_LLAX
t_LHLL
t_LLRL
t_CLLL
t_QVWH
t_WHQX
t_WLWH
t_WHLH
t_WHCH
t_RLRH
t_RLDV
t_RLDV1
t_RLDV1
t_RHDZ
t_CLYV
t_WLYZ
HYZ
t_RLYZ
t_RLYZ
t_WHDV
t_COPO
t_CHCL
Parameter
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
Address Valid to ale Low
Address Hold after ale Low
ale High Time
ale Low to rd_n Low
cs_n Low to ale Low
Data Setup to wr_n or wrh_n High
Input Data Hold after wr_n or wrh_n High
wr_n or wrh_n Pulse Width
wr_n or wrh_n High to Next ale High
wr_n or wrh_n High to cs_n High
rd_n Pulse Width. This time is long enough to initiate a double
read cycle by loading the High Speed Registers (04H, 05H), but is
too short to read from 04H and 05H (see t_RLDV).
rd_n Low to Data Valid (only for Registers 02H, 04H, 05H)
rd_n Low Data to Data Valid (for all Registers except 02H, 04H,
05H) for Read Cycle without a Previous Write^a
rd_n Low Data to Data Valid (for all Registers except 02H, 04H,
05H) for Read Cycle with a Previous Write
Data Float after rd_n High
cs_n Low to ready Setup (Load Capacitance on the ready Output
= 50 pF, V_OL = 1.0 V)
cs_n Low to ready Setup (Load Capacitance on the ready Output
= 50 pF, V_OL = 0.45 V)
wr_n or wrh_n Low to ready Float for a Write Cycle if No Previous
Write is Pending
End of Last Write to ready Float for a Write Cycle if a Previous
Write Cycle is Active^b
rd_n Low to ready Float (for all registers except 02H, 04H, 05H)
for Read Cycle without a Previous Write^a
rd_n Low to ready Float (for all registers except 02H, 04H, 05H)
for Read Cycle with a Previous Write
wr_n or wrh_n High to Output Data Valid on Port 1 or Port 2
clkout Period (CD_V is the value loaded in the CLKOUT Register
representing the clkout divisor)
clkout High Period (CD_V is the value loaded in the CLKOUT
Register representing the clkout divisor)
Minimum
8 MHz
4 MHz
2 MHz
7.5 ns
10 ns
30 ns
20 ns
10 ns
27 ns
10 ns
30 ns
8 ns
0 ns
40 ns
Maximum
16 MHz
10 MHz
8 MHz
–
–
–
–
–
–
–
–
–
–
–
0 ns
–
–
0 ns
–
55 ns
1.5 t_MCLK +
100 ns
3.5 t_MCLK +
100 ns
45 ns
32 ns
–
40 ns
–
145 ns
–
–
–
t_MCLK
(CD_V + 1) ×
t_OSC
(CD_V + 1) ×
½ t_OSC – 10
2 t_MCLK +
100 ns
2 t_MCLK +
100 ns
4 t_MCLK +
100 ns
2 t_MCLK +
500 ns
–
(CD_V + 1) ×
½ t_OSC + 15
a_{A “Read Cycle without a Previous Write” is where a read cycle follows a write cycle and there is greater}
than 2×t_MCLK between the rising edge of wr_n or wrh_n and the falling edge of rd_n.
b_{A “Previous Write Cycle is Active” is where the rising edge of wr_n or wrh_n for the second write is less}
than 2×t_MCLK after the rising edge of wr_n or wrh_for the first write.
IA211080504-07
Page 34 of 58
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