IA82527_13 Datasheet, PDF (43/58 Pages) InnovASIC, Inc – Serial Communications Controller—CAN Protocol

IA82527
CAN Serial Communications Controller
Data Sheet
December 20, 2012
Table 15. Mode 3: Asynchronous Operation Timing for 3.3V Operation
Symbol
1/t_XTAL
1/t_SCLK
1/t_MCLK
t_AVCL
t_CLDV
t_KLDV
t_CHDV
t_CHDH
t_CHDZ
t_CHKH1
t_CHKH2
t_CHKZ
t_CHCL
t_CHAI
t_CHRI
t_CLCH
t_DVCH
t_CLKL
t_CHKL
t_COPD
t_CHCL
Parameter
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
Address or r-w_n Valid to cs_n Low Setup
cs_n Low to Data Valid (for High-Speed Registers 02H, 04H,
and 05H)
cs_n Low to Data Valid (for Low-Speed Registers) Read
Cycle without Previous Write^a
cs_n Low to Data Valid (for Low-Speed Registers) Read
Cycle with Previous Write
dsack0_n Low to Output Data Valid (for High-Speed Read
Registers)
dsack0_n Low to Output Data Valid (for Low-Speed Read
Registers)
Input Data Hold after cs_n High
Output Data Hold after cs_n High
cs_n High to Output Data Float
cs_n High to dsack0_n = 2.4V (an on-chip pull-up will drive
dsack0_n to approximately 2.4V; an external pull-up is
required to drive this signal to a higher voltage)
cs_n High to dsack0_n = 2.8V
cs_n High to dsack0_n Float
cs_n Width between Successive Cycles
cs_n High to Address Invalid
cs_n High to r-w_n Invalid
cs_n Width Low
CPU Write Data Valid to cs_n High
cs_n Low to dsack0_n Low (for High- and Low-Speed
Registers) Write Cycle without Previous Write
End of Previous Write (cs_n High) to dsack0_n Low for a
Write Cycle with a Previous Write^b
clkout Period (CD_V is the value loaded in the CLKOUT
Register representing the clkout divisor)
clkout High Period (CD_V is the value loaded in the CLKOUT
Register representing the clkout divisor)
Minimum
8 MHz
4 MHz
2 MHz
3 ns
0 ns
0 ns
0 ns
–
0 ns
15 ns
0 ns
–
0 ns
Maximum
16 MHz
10 MHz
8 MHz
–
60 ns
1.5 t_MCLK +
100 ns
3.5 t_MCLK +
100 ns
35 ns
–
–
–
35 ns
55 ns
–
0 ns
25 ns
7 ns
6.5 ns
65 ns
20 ns
0 ns
150 ns
100 ns
–
–
–
–
–
67 ns
0 ns
2 t_MCLK + 145
ns
(CD_V + 1) × t_OSC
(CD_V + 1) ×
½ t_OSC – 10
(CD_V + 1) × ½
t_OSC + 15
a_{A “Read Cycle without Previous Write” is where a read cycle follows a write cycle and where the rising}
edge of cs_n for the write and the falling edge of cs_n for the read are separated by at least 2 × t_MCLK.
b_{A “Write Cycle with a Previous Write” is a write cycle following a previous write cycle where the rising}
edge of cs_n for the first write and the rising edge of cs_n for the second write are separated by at least
2 × t_MCLK.
IA211080504-07
Page 43 of 58
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