IA82527_13 Datasheet, PDF (29/58 Pages) InnovASIC, Inc – Serial Communications Controller—CAN Protocol

IA82527
CAN Serial Communications Controller
Data Sheet
December 20, 2012
4.1.1 CAN Controller
The CAN Controller block of the IA82527 supports the interface to the CAN Bus via the rx0,
rx1, tx0, and tx1 lines. The CAN Controller manages the transceiver logic, error management
logic, and the message objects, controlling the data stream between the Message RAM (parallel
data) and the CAN Bus (serial data).
4.1.2 Message RAM
The Message RAM block of the IA82527 provides the interface buffer between the system CPU
and the CAN Bus. The IA82527 Message RAM provides storage for 15 message objects of
8-byte data length. The Message RAM is Dual Port RAM allowing the CPU and the CAN
controller simultaneous access to the Message RAM.
4.1.3 CPU Interface
The IA82527 is can be interfaced to many commonly used microcontrollers. There are four
parallel interface options and a serial interface option.
Different interface options, or modes, are selected using interface mode pins, mode1 and mode0.
The parallel interface modes that can be selected are as follows:
• 8-bit Intel multiplexed address and data buses
• 16-bit Intel multiplexed address and data buses
• 8-bit non- Intel multiplexed address and data buses
• 8-bit non-multiplexed address and data buses
The serial interface mode is fully compatible with the Motorola^® SPI protocol and will interface
to most commonly used serial interfaces. The serial interface is implemented in slave mode
only, and responds to the master using the specially designed serial interface protocol. The serial
interface mode interconnection scheme is shown in Figure 6.
CPU
(Master)
MOSI
MISO
SCLK
CS
mosi
miso
sclk
cs_n
IA82527
(Slave)
Figure 6. mosi/miso Connection
IA211080504-07
Page 29 of 58
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