IA82527_13 Datasheet, PDF (22/58 Pages) InnovASIC, Inc – Serial Communications Controller—CAN Protocol

IA82527
CAN Serial Communications Controller
Data Sheet
December 20, 2012
Table 3. Pin/Signal Descriptions (Continued)
Signal
reset_n
Name
reset_n
Pin
PLCC
29
PQFP
23
Description
reset. Input. Active Low. When the reset_n signal is
asserted (low), the IA82527 is initialized. There are
two reset situations:
Cold reset is a power-on reset. As V_CC is driven to a
valid level (power on), the reset_n signal must be
driven low for a minimum of 1 ms measured from a
valid V_CC level. No falling edge on the reset_n pin is
required during a cold reset.
r-w_n
rx0
rx1
wr_n/wrl_n/r-w_n 7
rx0
22
rx1
21
For warm reset, V_CC remains at a valid level (i.e.,
power is already on and remains on) while reset_n is
driven low for a minimum of 1 ms.
1 read-write. Input. Active High (read)-Active Low
(write). Mode 2 and Mode 3. When r-w_n is high, it
signals a read cycle. When r-w_n is low, it signals a
write cycle.
16 Receive (rx), lines 0 and 1. Input. Pins rx0 and rx1
15 ^{are the inputs to the IA82527 from the CAN bus lines.}
These pins connect internally to the receiver input
comparator. Serial data from the CAN bus can be
received using both rx0 and rx1 or by using only rx0
as follows:
• When the CoBy Bit in the Bus Configuration
Register (2FH) is a 0, rx0 and rx1 are connected to
the input comparator rx0 is connected to the
non-inverting input and rx1 is connected to the
inverting input). A recessive level is read when rx0
> rx1. A dominant level is read when rx1 > rx0.
• When the CoBy Bit in the Bus Configuration
Register (2FH) is a 1, input comparison is disabled,
and rx0, which is still connected to the non-inverting
input of the comparator, is the CAN bus line input.
For this configuration, the DcR0 bit of the Bus
Configuration Register must be a 0.
After a cold reset (power on), the default configuration
is the use of both rx0 and rx1 for the CAN bus input.
sclk
a6/ad6/sclk
40
34 serial clock. Input. Serial Interface Mode. The sclk
pin is the serial clock input to the IA82527 (slave
device). The clock signal is provided by the master
device.
IA211080504-07
Page 22 of 58
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