IA8044_01 Datasheet, PDF (22/32 Pages) InnovASIC, Inc – SDLC COMMUNICATIONS CONTROLLER

IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
Frame Format Options
The various frame formats available with the IA8044/IA8344 are the standard SDLC format, the
no control field format, the no control field and no address field format and the no FCS field
format.
The standard SDLC format consists of an opening flag, an 8-bit address field, an 8-bit control
field, and n-byte information field, a 16-bit frame check sequence field and a closing flag. The
FCS is generated by the CCIT-CRC polynomial (X16 +X12 + X5 + 1). The address and control
fields may not be extended. The address is contained in STAD and the control filed is contained
in either RCB or TCB. This format is supported by both AUTO and FLEXIBLE modes.
The no control field format is only supported by the FLEXIBLE mode. In this format TCB and
RCB are not used and the information field starts immediately after the address field.
The no control field and no address field format is only supported by the FLEXIBLE mode. In
this format STAD, TCB and RCB are not used and the information field starts immediately after
the opening flag. This option can only be used with the no control field option.
The no FCS field format prevents an FCS from being generated during transmission or being
checked during reception. This option may be used in conjunction with the other frame format
options. This option will work with both FLEXIBLE and AUTO modes. In AUTO mode it
could cause protocol violations.
HDLC Restrictions
The IA8044/IA8344 supports a subset of the HDLC protocol. The differences include the
restriction by the IA8044/IA8344 of the serial data to be in 8-bit increments. In contrast HDLC
allows for any number of bits in the information field. HDLC provides an unlimited address field
and an extended frame number sequencing. HDLC does not support loop configuration.
SIU Details
The SIU is composed of two functional blocks with each having several sub blocks. The two
blocks are called the bit processor (BIP) and the byte processor (BYP).
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