IA8044_01 Datasheet, PDF (18/32 Pages) InnovASIC, Inc – SDLC COMMUNICATIONS CONTROLLER

IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
Serial Mode Register (SMD):
The serial mode register sets the operational mode of the SIU. The CPU can read and write SMD.
The SIU can read SMD. To prevent conflicts between CPU and SIU accesses to SMD the CPU
should write SMD only when RTS and RBE bits in the STS register are both zero. SMD is
normally only accessed during initialization. This register is byte addressable.
SMD (C9H)
Bit:
7
6
5
4
3
210
SCM2 SCM1 SCM0 NRZ LOO PFS NB NFCS
I
P
SMD.0
SMD.1
SMD.2
SMD.3
SMD.4
SMD.5
SMD.6
SMD.7
NFCS
NB
PFS
LOOP
NRZI
SCM0
SCM1
SCM2
When set selects No FCS field contained in the SDLC frame.
Non-buffered mode. No control field contained in SDLC frame.
Pre-frame sync mode. When set causes two bytes to be
transmitted before the first flag of the frame for DPLL
synchronization. If NRZI is set 00H is transmitted otherwise 55H.
This ensures that 16 transitions are sent.
When set selects loop configuration.
When set selects NRZI encoding otherwise NRZ.
Select clock mode - bit 0.
Select clock mode - bit 1.
Select clock mode - bit 2.
SMD Select Clock Mode Bits
SCM
210
000
001
010
011
100
101
110
111
Clock Mode
Data Rate
(Bits/sec)*
Externally clocked
0 – 2.4M**
Undefined
Self clocked, timer overflow 244 – 62.5K
Undefined
Self clocked, external 16X
0 – 375K
Self clocked, external 32X
0 – 187.5K
Self clocked, internal fixed
375K
Self clocked, internal fixed
187.5K
* based on a12 MHz crystal frequency
** 0 – 1M bps in loop configuration
Copyright © 2001
innovASIC
The End of Obsolescence™
ENG210010112-00
Page 18 of 32
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