IA8044_01 Datasheet, PDF (20/32 Pages) InnovASIC, Inc – SDLC COMMUNICATIONS CONTROLLER

IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
Send/Receive count register (NSNR):
The NSNR contains both the transmit and receive sequence numbers in addition to the tally error
indications. The CPU can read and write the STS. Accessing the STS by the CPU via 2 cycle
instructions (JBC bit,rel and MOV bit,C) should not be used. The SIU can read and write the
NSNR. NSNR is bit addressable.
NSNR (D8H)
Bit:
7
6
5
4
3
210
NS2 NS1 NS0 SES NR2 NR1 NR0 SER
NSNR.0
NSNR.1
NSNR.2
NSNR.3
NSNR.4
NSNR.5
NSNR.6
NSNR.7
SER
Sequence error receive. NS (P) ? NR (S).
NR0
Receive sequence counter, Bit 0.
NR1
Receive sequence counter, Bit 1.
NR2
Receive sequence counter, Bit 2.
SES
Sequence error send. NR (P) ? NS (S) and
NR (P) ? NS (S) + 1.
NS0
Send sequence counter, Bit 0.
NS1
Send sequence counter, Bit 1.
NS2
Send sequence counter, Bit 2.
Data Clocking Options
The SIU may be clocked in one of two ways, with an external clock or in a self-clocked mode.
In the external clocked mode a serial clock must be provided on SCLK. This clock must be
synchronized to the serial data. Incoming data is sampled at the rising edge of SCLK. Outgoing
data is shifted out at the falling edge of SCLK.
In the self-clocked mode the SIU uses a reference clock and the serial data to reproduce the serial
data clock. The reference clock can be an external source applied to SCLK, the IA8044/IA8344’s
internal clock or the timer 1 overflow. The reference clock must be 16x or 32x the data rate. A
DPLL uses the reference clock and the serial data to adjust the sample time to the center of the
serial bit. It does this by adjusting from a serial data transition in increments of 1/16 of a bit time.
The maximum data rate in the externally clocked mode is 2.4Mbps in half-duplex configuration
and 1.0Mbps in a loop configuration. The maximum data rate in the self-clocked mode with an
external clock is 375Kbps. The maximum data rate in the self-clocked mode with an internal
clock will depend on the frequency of the IA8044/IA8344’s input clock. An IA8044/IA8344
using a 12MHz input clock can operate at a maximum data rate of 375Kbps.
Copyright © 2001
innovASIC
The End of Obsolescence™
ENG210010112-00
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