IA8044_01 Datasheet, PDF (19/32 Pages) InnovASIC, Inc – SDLC COMMUNICATIONS CONTROLLER

IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
Status/Command Register (STS):
The Status/Command register provides SIU control from and status to the CPU. The SIU can
read the STS and can write certain bits in the STS. The CPU can read and write the STS.
Accessing the STS by the CPU via 2 cycle instructions (JBC bit,rel and MOV bit,C) should not be
used. STS is bit addressable.
STS (C8H)
Bit:
7
6
5
4
3
210
TBF RBE RTS SI BOV OPB AM RBP
STS.0
STS.1
STS.2
STS.3
STS.4
STS.5
STS.6
STS.7
RBP
AM
OPB
BOV
SI
RTS
RBE
TBF
Receive buffer protect. When set prevents writing of data into
the receive buffer. Causes RNR response instead of RR in AUTO
mode.
Auto mode. If NB is cleared AM selects the AUTO mode when
set. If NB is set AM selects the addressed mode when set. The SIU
can clear AM.
Optional poll bit. When set the SIU will AUTO respond to an
optional poll (UP with P=0). The SIU can set or clear the OPB.
Receive buffer overrun. The SIU can set or clear BOV.
SIU interrupt. This bit is set by the SIU and should be cleared
by the CPU before returning from the interrupt routine.
Request to send. This bit is set when the SIU is ready to
transmit or is transmitting. May be written by the SIU in AUTO
mode.
Receive buffer empty. RBE is set by the CPU when it is ready to
receive a frame or has just read the buffer. It is cleared by the SIU
when a frame has been received.
Transmit buffer full. TBF is set by the CPU to indicate that the
transmit buffer is ready and cleared by the SIU.
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The End of Obsolescence™
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