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XC2734X_13 Datasheet, PDF (99/106 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance
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XC2734X
XC2000 Family / Value Line
Electrical Parameters
Table 35 JTAG Interface Timing for Upper Voltage Range (cont’d)
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
TCK low time
t3 SR 16
−
−
ns
TCK clock rise time
t4 SR −
−
8
ns
TCK clock fall time
t5 SR −
−
8
ns
TDI/TMS setup to TCK t6 SR 6
−
−
ns
rising edge
TDI/TMS hold after TCK t7 SR 6
−
−
ns
rising edge
TDO valid from TCK falling t8 CC −
edge (propagation delay)2)
25
29
ns
TDO high impedance to t9 CC −
valid output from TCK
falling edge3)2)
25
29
ns
TDO valid output to high t10 CC −
impedance from TCK
falling edge2)
25
29
ns
TDO hold after TCK falling t18 CC 5
−
−
ns
edge2)
1) Under typical conditions, the JTAG interface can operate at transfer rates up to 20 MHz.
2) The falling edge on TCK is used to generate the TDO timing.
3) The setup time for TDO is given implicitly by the TCK cycle time.
Table 36 is valid under the following conditions: CL= 20 pF; voltage_range= lower
Table 36 JTAG Interface Timing for Lower Voltage Range
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
TCK clock period
t1 SR 50
−
−
ns
TCK high time
t2 SR 16
−
−
ns
TCK low time
t3 SR 16
−
−
ns
TCK clock rise time
t4 SR −
−
8
ns
TCK clock fall time
t5 SR −
−
8
ns
TDI/TMS setup to TCK t6 SR 6
−
−
ns
rising edge
Data Sheet
99
V1.5, 2013-02
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