XC2734X_13 Datasheet, PDF (96/106 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2734X
XC2000 Family / Value Line
Electrical Parameters
4.7.6 Debug Interface Timing
The debugger can communicate with the XC2734X either via the 2-pin DAP interface or
via the standard JTAG interface.
Debug via DAP
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 33 is valid under the following conditions: C_L= 20 pF; voltage_range= upper
Table 33 DAP Interface Timing for Upper Voltage Range
Parameter
DAP0 clock period¹⁾
DAP0 high time
DAP0 low time¹⁾
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup to DAP0
rising edge
Symbol
Min.
t₁₁ SR 25
t₁₂ SR 8
t₁₃ SR 8
t₁₄ SR −
t₁₅ SR −
t₁₆ SR 6
Values
Typ. Max.
−
−
−
−
−
−
−
4
−
4
−
−
Unit Note /
Test Condition
ns
ns
ns
ns
ns
ns
DAP1 hold after DAP0 t₁₇ SR 6
−
−
ns
rising edge
DAP1 valid per DAP0
t₁₉ CC 17
20
−
ns
clock period²⁾
1) See the DAP chapter for clock rate restrictions in the Active::IDLE protocol state.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
Table 34 is valid under the following conditions: C_L= 20 pF; voltage_range= lower
Data Sheet
96
V1.5, 2013-02