XC228X Datasheet, PDF (98/110 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

Preliminary
XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Electrical Parameters
Table 23
External Bus Cycle Timing for 3.0 V ≤ V_DDP ≤ 4.5 V
(Operating Conditions apply)
Parameter
Symbol
Limits
Unit Note
Min. Typ. Max.
Output valid delay for:
RD, WR(L/H)
tc₁₀ CC –
20 ns
Output valid delay for:
BHE, ALE
tc₁₁ CC –
20 ns
Output valid delay for:
tc₁₂ CC –
A23 … A16, A15 … A0 (on P0/P1)
22 ns
Output valid delay for:
A15 … A0 (on P2/P10)
tc₁₃ CC –
22 ns
Output valid delay for:
CS
tc₁₄ CC –
20 ns
Output valid delay for:
tc₁₅ CC –
D15 … D0 (write data, MUX-mode)
21 ns
Output valid delay for:
D15 … D0 (write data, DEMUX-
mode)
tc₁₆ CC –
21 ns
Output hold time for:
RD, WR(L/H)
tc₂₀ CC 0
10 ns
Output hold time for:
BHE, ALE
tc₂₁ CC 0
10 ns
Output hold time for:
tc₂₃ CC 0
A23 … A16, A15 … A0 (on P2/P10)
10 ns
Output hold time for:
CS
tc₂₄ CC 0
10 ns
Output hold time for:
D15 … D0 (write data)
tc₂₅ CC 0
10 ns
Input setup time for:
READY, D15 … D0 (read data)
tc₃₀ SR 29
–
ns
Input hold time for:
READY, D15 … D0 (read data)¹⁾
tc₃₁ SR -6
–
ns
1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read
data can be removed after the rising edge of RD.
Data Sheet
96
V0.91, 2007-02
Draft Version