XC228X Datasheet, PDF (36/110 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3
Functional Description
The architecture of the XC228x combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resources as well as external
resources (see Figure 3). This bus structure enhances the overall system performance
by enabling the concurrent operation of several subsystems of the XC228x.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC228x.
PSR A M
16/32/64 Kbytes
Program Flash 0
256 Kbytes
Program Flash 1
192/256 Kbytes
Program Flash 2
0/64/256 Kbytes
D PR A M
2 Kbytes
D SR A M
16 Kbytes
CPU
C166SV2 - Core
Oscillators/PLL, System Fct.
Clock, Reset, Power Control,
Stand-By RAM
Interrupt & PEC
Interrupt Bus
OCDS
Debug Support
EB C
LXBus Control
External Bus
C o n tro l
WDT
RTC
ADC1 ADC0
8-Bit/ 8-Bit/
10-Bit 10-Bit
8 Ch. 16 Ch.
GPT
T2
T3
T4
... _{CC2 CCU63 CCU60}
T7 T12
T12
T8 T13
T13
T5
BRTG6en
USIC2 USIC1 USIC0
2 Ch., 2 Ch., 2 Ch.,
64 x 64 x 64 x
Buffer Buffer Buffer
M ulti
CAN
RS232, RS232, RS232,
LIN,
SPI,
LIN,
SPI,
LIN,
SPI,
2 /5 ch .
IIC, IIS IIC, IIS IIC, IIS
P1 5
Port 5
P1 1
8
16
6
P1 0
16
P9 P8 P7 P6 P4 P3
8
7 54 8
8
P2
P1 P0
13
8
8
Figure 3 Block Diagram
MC_XC2X_BLOCKDIAGRAM
Data Sheet
34
V0.91, 2007-02
Draft Version