C161U Datasheet, PDF (93/469 Pages) Infineon Technologies AG – Embedded C166 with USB, USART and SSC

C161U
Central Processor Unit
For each pair of linked channels, an internal channel flag, the Channel Link Toggle flag
Table 12
PEC Channels which could be linked together
Linked PEC Channels
PEC Channel
A
channel 0
channel 2
channel 4
channel 6
PEC Channel
B
channel 1
channel 3
channel 5
channel 7
Linked PEC Channel
channel 0
channel 2
channel 4
channel 6
CLT identifies which of the two PEC channels will serve the next PEC request. The CLT
flag is indicated in both PECCx registers of two linked PEC channels, where the CLT bit
in channel B always is inverse to the CLT bit in channel A. The very first transfer is
always started with the channel A if the CLT bit was not programmed otherwise before.
The CLT bit is only valid in case of linked PEC channels, indicated by the CL bits of linked
channels. If linking is not enabled, the CLT bit of both channels is always zero
(compatibility!).
The internal channel link flag CLT toggles, and the other channel begins service with the
next request if the "old" channel stops the service (COUNT=0 or COUNT2=0, dependent
on the mode), and if the new channel has in its PEC control register the CL flag enabled
and its transfer count is more than zero. Note: With the last transfer of a block transfer
(COUNT=0 or COUNT2=0), the channel link control flag CL of that channel is cleared in
its PECCx register. If the channel link flag CL of the new (chained) PEC control register
is found to be zero the whole data transfer is finished and the channel link interrupt is
coincidently a termination interrupt. The channel link mode is finished and the internal
channel toggle flag is cleared after the last transfer of the block, if the CL flags of both
pair channels are cleared.
Data Sheet
93
2001-04-19