C161U Datasheet, PDF (316/469 Pages) Infineon Technologies AG – Embedded C166 with USB, USART and SSC

C161U
High-Speed Synchronous Serial Interface
content of the timer. Reading SSCBR, while the SSC is disabled, returns the
programmed reload value. In this mode the desired reload value can be written to
SSCBR.
Note: Never write to SSCBR, while the SSC is enabled.
The formulas below calculate either the resulting baud rate for a given reload value, or
the required reload value for a given baudrate:
f_CPU
B_SSC = _{2 * (<SSCBR> + 1)}
f_CPU
SSCBR = (
)-1
2 * Baudrate_SSC
<SSCBR> represents the content of the reload register, taken as unsigned 16-bit
integer.
The maximum baud rate that can be achieved when using a CPU clock of 36 MHz is 18
MBaud in SSC Master Mode (<SSCBR>= ’0_d’), while in SSC Slave Mode the maximum
baud rate is 9 MBaud (<SSCBR>= ’1_d’ since <SSCBR>=’0_d’ is not allowed in Slave
Mode). The minimum baud rate is 274.66 Baud (<SSCBR> = ’FFFF_H’ = ’65535_D’).
14.4
Error Detection Mechanisms
SSC is able to detect four different error conditions. Receive Error and Phase Error are
detected in all modes, while Transmit Error and Baudrate Error only apply to slave mode.
When an error is detected, the respective error flag is set. When the corresponding Error
Enable Bit is set, also an error interrupt request will be generated by setting SSCEIR (see
figure below). The error interrupt handler may then check the error flags to determine the
cause of the error interrupt. The error flags are not reset automatically (like SSCEIR), but
rather must be cleared by software after servicing. This allows servicing of some error
conditions via interrupt, while the others may be polled by software.
Note: The error interrupt handler must clear the associated (enabled) errorflag(s) to
prevent repeated interrupt requests.
A Receive Error (Master or Slave mode) is detected, when a new data frame is
completely received, but the previous data was not read out of the receive buffer register
SSCRB. This condition sets the error flag SSCRE and, when enabled via SSCREN, the
error interrupt request flag SSCEIR. The old data in the receive buffer SSCRB will be
overwritten with the new value and is unretrievably lost.
A Phase Error (Master or Slave mode) is detected, when the incoming data at pin MRST
(master mode) or MTSR (slave mode), sampled with the same frequency as the CPU
clock, changes between one sample before and two samples after the latching edge of
the clock signal (see “Clock Control”). This condition sets the error flag SSCPE and,
when enabled via SSCPEN, the error interrupt request flag SSCEIR.
Data Sheet
316
2001-04-19