C161U Datasheet, PDF (190/469 Pages) Infineon Technologies AG – Embedded C166 with USB, USART and SSC

Segment
ALE
BUS (P0)
RD
Address
Bus Cycle
Address
C161U
External Bus Interface
Data/Instr.
BUS (P0)
Address
Data
WR
MCTC Wait States (1...15)
MCT02063
Figure 49 Memory Cycle Time
The external bus cycles of the C161U can be extended for a memory or peripheral, which
cannot keep pace with the controller’s maximum speed, by introducing wait states during
the access (see figure above). During these memory cycle time wait states, the CPU is
idle, if this access is required for the execution of the current instruction.
The memory cycle time wait states can be programmed in increments of one CPU clock
within a range from 0 to 15 (default after reset) via the MCTC fields of the BUSCON
registers. 15-<MCTC> waitstates will be inserted.
Programmable Memory Tri-State Time
C161U allows the user to adjust the time between two subsequent external accesses to
account for the tri-state time of the external device. The tri-state time defines, when the
external device has released the bus after deactivation of the read command (RD).
Data Sheet
190
2001-04-19