C161U Datasheet, PDF (307/469 Pages) Infineon Technologies AG – Embedded C166 with USB, USART and SSC

C161U
High-Speed Synchronous Serial Interface
SSCCON (FFB2_H / D9_H)
15 14 13 12 11 10 9
SFR
87
SSC SSC
SSC SSC SSC SSC SSC
EN=0 MS ^- AREN BEN PEN REN TEN ^-
654
SSC SSC SSC
PO PH HB
Reset Value: 0000_H
3210
SSCBM
rw rw - rw rw rw rw rw - rw rw rw
rw
Bit
SSCBM
SSCHB
SSCPH
SSCPO
SSCTEN
SSCREN
SSCPEN
SSCBEN
SSCAREN
SSCMS
SSCEN
Function (Programming Mode, SSCEN = ‘0’)
SSC Data Width Selection
0 : Reserved. Do not use this combination.
1...15 : Transfer Data Width is 2...16 bit (<SSCBM>+1)
SSC Heading Control Bit
0 : Transmit/Receive LSB First
1 : Transmit/Receive MSB First
SSC Clock Phase Control Bit
0 : Shift transmit data on the leading clock edge, latch on trailing edge
1 : Latch receive data on leading clock edge, shift on trailing edge
SSC Clock Polarity Control Bit
0 : Idle clock line is low, leading clock edge is low-to-high transition
1 : Idle clock line is high, leading clock edge is high-to-low transition
SSC Transmit Error Enable Bit
0 : Ignore transmit errors
1 : Check transmit errors
SSC Receive Error Enable Bit
0 : Ignore receive errors
1 : Check receive errors
SSC Phase Error Enable Bit
0 : Ignore phase errors
1 : Check phase errors
SSC Baudrate Error Enable Bit
0 : Ignore baudrate errors
1 : Check baudrate errors
SSC Automatic Reset Enable Bit
0 : No additional action upon a baudrate error
1 : The SSC is automatically reset upon a baudrate error
SSC Master Select Bit
0 : Slave Mode. Operate on shift clock received via SCLK.
1 : Master Mode. Generate shift clock and output it via SCLK.
SSC Enable Bit = ‘0’
Transmission and reception disabled. Access to control bits.
Data Sheet
307
2001-04-19