C161U Datasheet, PDF (345/469 Pages) Infineon Technologies AG – Embedded C166 with USB, USART and SSC

C161U
USB Interface Controller
Table 88 USBD_CFGVAL_REG Command Register
Bit No. Bit
Function
5:4
AS_IF1
Alternate Setting selected for Interface 1:
’xx’: Alternate Setting 3-0 binary coded.
(read-only)
3:2
AS_IF0
Alternate Setting selected for Interface 0:
’xx’: Alternate Setting 3-0 binary coded.
(read-only)
1:0
CFG
Configuration selected by host
’xx’:Configuration 2-0 binary coded.
(read-only)
The USBD CFGVAL register provides the current selection of the configuration and
alternate setting done by the host. The SET_CONFIGURATION resets all settings to
Alternate Setting 0, i.e. the Control Endpoint 0.
USBC_CMD_RESET Reset Value: 0000_H
Table 89 USBC_CMD_RESET USB RESET REGISTER
Bit No. Bit
Function
(15:1) Reserved
reserved
(0)
USBC_RST
Resets the USB block including the transmit and
receive logic. The USB RESET does not reset the
USBCLC register. The USB reset must be active for
at least 10 clock cycles. The USB reset must always
be activated after the USB device is connected to
the USB
15.7
Programmers Guidlines: Using USB and EPEC
For normal functionality, the following interrupts must be enabled:
all udc_tx_done- and udc_rx_done-interrupts of those endpoints and in the direction in
which they are used
udc_setup, udc_suspend, udc_suspendoff, udc_start of frame, udc_configval
optional interrupts are the EPEC-interrupt (this interrupt might only be used if SW needs
to have complete control over the contents of the fifos and always wants to keep track of
the status of the transmission) and the UDC_txwr- and UDC_rxrr-interrupts (which are
generated every time, a fifo in the USB-block is ready to accept data or receive-data
Data Sheet
345
2001-04-19