C161U Datasheet, PDF (467/469 Pages) Infineon Technologies AG – Embedded C166 with USB, USART and SSC

C161U
AC/DC Characteristics
2) _{Demultiplexed bus is the worst case. For multiplexed bus, 2 TCL is to be added to the maximum values. This}
adds even more time for deactivating READY.
Note: The 2t_A and t_C refer to the next following bus cycle, t_F refers to the current bus
cycle.
Running cycle 1)
READY
waitstate
MUX/Tristate 6)
t₃₂
t₃₃
CLKOUT
t₃₀
t₃₄
t₃₁
t₂₉
ALE
7)
Command RD, WR
2)
t₃₅
t₃₆
t₃₅
t₃₆
Sync
READY
3)
3)
t₅₈
t₅₉
t₅₈
t₅₉
t₆₀ 4)
Async
READY
3)
3)
t₃₇
5)
see 6)
Figure 138 CLKOUT and READY
1) _{Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).}
2) _{The leading edge of the respective command depends on RW-delay.}
3) _{READY sampled HIGH at this sampling point generates a READY controlled wait state. READY sampled}
LOW at this sampling point terminates the bus cycle currently running.
4) _{READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or}
WR).
5) _{If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT}
(eg. because
if READY is
CLKOUT
removed
is
in
rneoptoennsaebtloedth),eitcmomusmt afunldfill(s^t3e⁷einNoortdee^4r))t.o
be
safely
synchronized.
This
is
guaranteed
6) _{Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state may}
be inserted here. For a multiplexed bus with MTTC wait state, this delay is 2 CLKOUT cycles, for a
demultiplexed bus without MTTC wait state this delay is zero.
7) _{The next external bus cycle may start here.}
Data Sheet
467
2001-04-19