1EDI30J12CP Datasheet, PDF (9/28 Pages) Infineon Technologies AG – 1EDI EiceDRIVER™ Enhanced

EiceDRIVER™ Enhanced
1EDI30J12CP
Functional Description
3.2.1 Supply options
Two different isolated supply configurations are possible depending on the reference node of the supply.
1. The external power supply is related to VCC2 (see Figure 3 high-side switch and Figure 10).
This configuration is possible for both high and low-side switches, but each driver has to be separately supplied
in order to guarantee the correct start up behavior. It is not possible to share the same supply among more
than one driver.
2. The external power supply is related to the MOSFET drain potential (see Figure 3 low-side switches and
Figure 12).
This allows for using the same power supply to more than one driver stage as long as their MOSFET drains
are connected to the same potential. Which makes this configuration most suitable to be used on drivers
connected to low-side switches.
HV supply
L1
+5V
VCC1 JFDrv
CVCC1
N
VCC2
GND
HS_IN
GND1 MDrv
EN
VReg
IN
CLJFG
VEE2
BSEN
CVReg
CVEE2
C
-25V_HS
Load
1EDI30J12Cx
+5V
CVCC1
GND
PFC_IN
VCC1 JFDrv
VCC2
GND1 MDrv
EN
VReg
IN
CLJFG
VEE2
BSEN
1EDI30J12Cx
CVReg
CVEE2
+5V
CVCC1
GND
LS_IN
VCC1 JFDrv
VCC2
GND1 MDrv
EN
VREG
IN
CLJFG
VEE2
BSEN
1EDI30J12Cx
CVReg
CVEE2
C
-25V
Figure 3 Application drawing for isolated supply (PFC+HB)
Additionally it is possible to supply the driver via bootstrapping. In this supply mode a high-side driverstage can
share the same isolated high-side supply (see Figure 6). It is also possible to transfer the power from the high-
side to a low-side driverstage via a bootrapping capacitor (see Figure 13). Further information about the
bootstapping supply can be found in Chapter 3.2.4.
3.2.2 Normal start up
This section describes a normal start up in which the auxiliary supplies of the driver are enabled before a voltage
is applied over the switch (JFET drain to pMOS drain). The timing diagram of this start up is shown in Figure 4.
The negative driver supply voltage is applied to VEE2. VREG is following the supply voltage ramp with the
regulator drop of approximately 2V, depending on the capacitor size and the ramping speed of VEE2. When VREG
reaches the UVLO threshold the driver is turning on the p-channel MOSFET. After MDrv has reached the on-
threshold the JFET gate driver stage is active and follows the IN signals with a short propagation delay of typical
80ns.
Preliminary Datasheet
8
Rev. 1.3, 2014-11-12