1EDI30J12CP Datasheet, PDF (8/28 Pages) Infineon Technologies AG – 1EDI EiceDRIVER™ Enhanced

3
Functional Description
EiceDRIVER™ Enhanced
1EDI30J12CP
Functional Description
3.1
Introduction
The 1EDI30J12Cx is an advanced JFET (junction gate field-effect transistor) gate driver. The driver is built to drive
a normally-on CoolSiC^TM JFET together with a low voltage p-channel MOSFET in a switching loss optimized
cascode operation called Direct Drive JFET Topology.
As MOSFET (metal–oxide–semiconductor field-effect transistor; referred to as pMOS, LV MOSFET) a 30 V p-
channel OptiMOS^TM MOSFET with low R_DSon is typically used (e.g. OptiMOS^TM BSC030P03NS3 G).
The driver consists of two galvanic separated parts. The inputs can be connected to any controller with varying
signal levels. The pins can handle signals up to 17.5V, however the thresholds remains at TTL levels.
The output side is connected to the high voltage side of the application, incorporates two rail to rail output stages.
The two gate drivers, one for the JFET and one for the MOSFET, drive the gates between VCC2 and the regulated
output VREG.
The 1EDI30J12Cx supports two different start up modes selectable by the bootstrap enable pin BSEN. A
specialized bootstrap operation mode for supplying the driver via a bootstrap diode. And a standard operation
mode for direct supply realised with a floating isolated supply source.
The output side has a built in linear voltage regulator to generate an accurate JFET driver supply voltage inside
the window between pinch off voltage and punch through voltage of Infineon’s CoolSiC^TM JFETs . In addition, the
internal regulator separates the driver supply voltage from a common supply voltage for low side switches, so all
low side switches could be supplied by one negative supply. Further in isolated supply topologies it offers the
support of wide supply range due to preregulation. So voltage drops due to bad transformer coupling can be
handled.
Cascodes were introduced in the past for faster switching made possible by the elimination of the JFETs Cgd
acting as a feedback to the control gate. The disadvantage by eliminating the feedback is that the dV/dt of the
switch gets uncontrolled.
New JFET devices like CoolSiC^TM JFET offers a reduced gate charge, therefore driving the JFET gate directly
offers advantages in controlling the switching speed with lower EMI and less ringing.
3.2
Theory of Operation
The optimized cascode operation offered by the 1EDI30J12Cx driver called Direct Drive JFET Topology differs
from the normal cascode in the way it is controlling the switch. The normal cascode controls the normally-on JFET
by indirectly controlling the source potential of the JFET via the low-voltage MOSFET.
In the Direct Drive JFET Topology the MOSFET is used to keep the normally-on JFET in a safe off-state during
start up of the application as in the normal cascode. When the driver auxilliary supply voltage is high enough to
release the Under Voltage Lock Out (UVLO) the MOSFET is permanently turned on and the JFET is driven directly
according to the input signal.
The input signal is transferred across the isolating Coreless Transformer (CLT) from input side to output side. A
high at the input pin turns on the JFET. The 1EDI30J12Cx is a non inverting driver.
When the VCC1 supply voltage has reached the turn on threshold and the signal at the EN pin is high, the input
side is able to send the IN signal to the output side.
Depending on the UVLO of the output side, the input signal is either ignored if |V_VREG| is below the UVLO-on-
threshold or is applied amplified at the gate of JFET.
When the VCC1 voltage potential reaches the turn off threshold, the input side sends an off signal to the output
side to ensure a defined switch off state before the driver is disabled.
The driver can be disabled using the EN pin: in case the EN pin is pulled to low, the output is switched off
regardless of the signal applied to the IN pin.
Preliminary Datasheet
7
Rev. 1.3, 2014-11-12